Lexicon
6-9
Here is how this area is mapped:
ADDRESS VIEW FROM Z80
RAM_A14 = 0
VIEW FROM Z80
RAM_A14 = 1
VIEW FROM 2186
0x4000 SRAM LOAD SRAM
0x4400 (used by 2186 (used during
0x4800 during boot and boot and
0x4C00 program load) UPPER HALF program load)
0x5000 LEXICHIP OF SRAM
0x5400 FPGA UART (used for
0x5800 FPGA REG 1 preset
0x5C00 FPGA REG 2 storage)
0x6000 SRAM SHARED SRAM SHARED
0x6400 WITH 2186 WITH Z80
0x6800 FPGA REG 1
0x6C00 SRAM FPGA REG 2
0x7000 LEXICHIP
0x7400 FPGA UART
0x7800 2186 INTERNAL
0x7C00 RAM/REGISTERS
The peripherals are mapped into different addresses for the Z80 and the 2186 so that each processor can
maximize its usage of the SRAM. The 2186 boots from the low 4K of the SRAM.
The 8K chunk of SRAM starting at 0x6000 is used by the Z80 for general storage. The lowest 2K of this
chunk is visible by both the Z80 and the 2186. The Z80 must keep variables which must be visible to the
2186 in this area.
When the RAM bank select line (RAM_A14) is high, the entire 16K block from 0x4000 to 0x7FFF is mapped
to the upper half of SRAM, which the Z80 will use to store user preset data. Because the Z80's stack is
invisible when RAM_A14 is high, the Z80 must be careful to disable interrupts when accessing upper RAM.
The FPGA has two internal 8-bit registers (reg1 and reg2).
REGISTER 1 (write only):
bit 0 SAVE_SRAM. When 1, it prevents the DSP from writing to the low byte of the SRAM. The Z80
asserts this bit when preparing to load a new program into the DSP. This prevents the DSP from
overwriting the program with audio data.
bit 2 ENABLE_NMI. When 1, enables the NMI output. The rate is set by the “SPEAKER” register. The
divisor divides the master clock (22.58 MHz / 256). "0" gives 3 mS and 255 will get 11 S, and so on.
To Next Page
Loading...
Need help?
General
