Marantz SA-7S1f - Page 24

1-361-35
CLOCK
GEN
INTERNAL
DATA BUS
SWITCH
EXT AL
PROGRAM
RAM
0.5 K x 24
PROGRAM ROM
8K x2 4
Bootstrap ROM
192 x 24
PROGRAM
INTERRUPT
CONT
PR OGRAM
DECODE
CONT
PROGRAM
ADDRESS
GEN
YA B
XAB
PA B
YD B
XD B
PD B
GD B
M O DA /IRQ A
M O DB /IRQ B
DATA ALU
24 X24
+
56
56-BIT MAC
TWO 56-BITACCUM ULATORS
BARREL SHIFTER
MODD/IRQ D
PLL
ADDRESS
GENERATION UNIT
OnCEô
DSP56300
GPIO
ESAI
12
4
24-BIT
X
MEMORY
RAM
1K X24
Y MEMORY
RAM
1.5K X 24
DDB
DA B
SIX CHANNELS
DMA UNIT
CORE
YM _ EB
XM _ EB
PM_EB
PIO_EB
24 BITS BUS
SHI
JTAG
4
5
RESET
POWER
MGMT
PINIT/ NM I
DRAM & SRAM
BUS
INTERFACE
EXTERNAL
ADDRESS BUS
SWITCH
EXTERNAL
DATA BUS
SWITCH
6
8
18
PERIPHERAL
EXPANSION
AREA
MEMOR Y
EXPANSION
AREA
ADDRESS
CONTROL
DATA
→
NJM2880U
V
OUT
GND
V
IN
Thermal
Protection
Bandgap
Reference
Noise
Bypass
Cont
PIN FUNCTION
1.CONTROL (Active High)
2.GND
3.NOISE BYPASS
4.V
OUT
5.V
IN
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Pin Name Function
A0 - A18 Addresses
CE
Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(496K BYTES)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
04000H
03FFFH
00000H
7FFFFH
1
2
3
6
4
5
7
8
1. NC
2. DRAIN 2
3. GATE 2
4. SOURCE 2
5. SOURCE 1
6. GATE 1
7. DRAIN 1
8. SUBSTRAIGHT
(SUBSTRAIGHT: OPEN)
Q114 : AT49BV040B Q111 : DSP56364UM (PEC777f2)
Q107 : NJM2880
Q211 : 2SK389FM
Q202 : NJM2887