viii List of Figures
List of Figures
Figure 2-1. DC Power Distribution........................................................................................................... 2-2
Figure 3-1. APX 2000/ APX 4000/ APX 4000Li Overall Block Diagram .................................................. 3-2
Figure 3-2. APX 1000 (900 MHz) Overall Block Diagram ....................................................................... 3-3
Figure 3-3. Transceiver (VHF) Block Diagram (Power and Control Omitted).......................................... 3-4
Figure 3-4. Transceiver (UHF1/UHF2) Block Diagram (Power and Control Omitted) ............................. 3-5
Figure 3-5. Transceiver (700/800 MHz) Block Diagram (Power and Control Omitted) ........................... 3-6
Figure 3-6. Transceiver (900 MHz) Block Diagram (Power and Control Omitted) .................................. 3-7
Figure 3-7. Receiver Block Diagram (VHF) ............................................................................................. 3-8
Figure 3-8. Receiver Block Diagram (UHF1/UHF2) ................................................................................ 3-9
Figure 3-9. Receiver Block Diagram (700/800 MHz ).............................................................................. 3-9
Figure 3-10. Receiver Block Diagram (900 MHz )..................................................................................... 3-9
Figure 3-11. Transmitter Block Diagram (VHF/UHF1/UHF2/900 MHz)................................................... 3-11
Figure 3-12. Transmitter Block Diagram (700/800 MHz)......................................................................... 3-12
Figure 3-13. Synthesizer Block Diagram (VHF) ...................................................................................... 3-16
Figure 3-14. Synthesizer Block Diagram (UHF1/UHF2).......................................................................... 3-17
Figure 3-15. Synthesizer Block Diagram (700/800 MHz) ........................................................................ 3-17
Figure 3-16. Synthesizer Block Diagram (900 MHz) ............................................................................... 3-18
Figure 3-17. Controller Interconnection Diagram .................................................................................... 3-23
Figure 3-18. Controller Electrical Overview ............................................................................................. 3-25
Figure 3-19. Controller DC Block Diagram .............................................................................................. 3-26
Figure 3-20. V_SW_1.4 Switched Power Supply .................................................................................... 3-29
Figure 3-21. 5V Switched Power Supply ................................................................................................. 3-30
Figure 3-22. Power-up Timing Regulators............................................................................................... 3-31
Figure 3-23. Controller Clock Architecture .............................................................................................. 3-32
Figure 3-24. Overview of OMAP Interconnection with Controller Peripherals......................................... 3-34
Figure 3-25. OMAP Memory Interface..................................................................................................... 3-35
Figure 3-26. RX/ TX SSI Configuration ................................................................................................... 3-36
Figure 3-27. Audio SSI Configuration...................................................................................................... 3-37
Figure 3-28. SPI and I2C Configuration .................................................................................................. 3-38
Figure 3-29. CPLD Block Diagram .......................................................................................................... 3-39
Figure 3-30. Audio TX Path Block Diagram............................................................................................. 3-40
Figure 3-31. RX Audio Path Block Diagram ............................................................................................ 3-41
Figure 3-32. Control Top Block Diagram (APX 2000/ APX 4000/ APX 4000Li/ APX 1000 (900 MHz))... 3-42
Figure 3-33. Control Top Block Diagram (APX 2000/ APX 4000 (Two Knobs)) ...................................... 3-43
Figure 3-34. Display Circuit Detail Overview Block Diagram................................................................... 3-44
Figure 3-35. Lighting Controller Overview ............................................................................................... 3-46
Figure 3-36. Keypad Interface Outline..................................................................................................... 3-47
Figure 3-37. GCAI Signal Configuration .................................................................................................. 3-48
Figure 3-38. GCAI Connector.................................................................................................................. 3-49
Figure 3-39. APX 2000/ APX 4000 Encryption Architecture.................................................................... 3-51
Figure 3-40. GPS Block Diagram ............................................................................................................ 3-54
Figure 3-41. Accelerometer Block Diagram............................................................................................. 3-55
Figure 3-42. Relation of Bluetooth & LF Antenna Assembly to Main & Keypad Boards ......................... 3-57
Figure 3-43. Bluetooth Connection Flowchart ......................................................................................... 3-58
Figure 3-44. Bluetooth/Controller Interface with Clock Sources.............................................................. 3-59
Figure 3-45. Bluetooth Functional Block Diagram ................................................................................... 3-59
Figure 3-46. Bluetooth Low-Frequency Circuit Block Diagram................................................................ 3-60
Figure 3-47. Bluetooth Low-Frequency Pairing Data Path ...................................................................... 3-60
Figure 3-48. Detailed Low-Frequency Transmit/Receive Paths .............................................................. 3-61
Figure 3-49. Chip Power-Up/Power-Down Sequence (Exernal Input/Output Shown)............................. 3-61
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