Troubleshooting Tables: List of Board and IC Signals 7-27
cpld_ver3 CPLD version identifier
bit 3
(REG) Register Register
cpld_ver2 CPLD version identifier
bit 2
(REG) Register Register
cpld_ver1 CPLD version identifier
bit 1
(REG) Register Register
cpld_ver0 CPLD version identifier
bit 0
(REG) Register Register
board_id8 Controller Board ID bit 8 H12 Input Pul-
lup
Input Pul-
lup
board_id7 Controller Board ID bit 7 H13 Input Pul-
lup
Input Pul-
lup
board_id6 Controller Board ID bit 6 G13 Input Pul-
lup
Input Pul-
lup
board_id5 Controller Board ID bit 5 F13 Input Pul-
lup
Input Pul-
lup
board_id4 Controller Board ID bit 4 D13 Input Pul-
lup
Input Pul-
lup
board_id3 Controller Board ID bit 3 E13 Input Pul-
lup
Input Pul-
lup
board_id2 Controller Board ID bit 2 C14 Input Pul-
lup
Input Pul-
lup
board_id1 Controller Board ID bit 1 D14 Input Pul-
lup
Input Pul-
lup
board_id0 Controller Board ID bit 0 F14 Input Pul-
lup
Input Pul-
lup
none OMAP GPIO1 deter-
mines default state of
some EMIFS pins.
Latched on rising edge
of PWR_ON_RESET.
Pulled low on PCB
R19 Input Pull-
down
0 Input Pull-
down
none "Unused, defaults to
UART2.BCLK in reset
mode 0. Pulldown on
PCB
"Y4 Output None 0 Output None
Table 7-10. Overall GPIO pin functions (Continued)
Signal Name Description
Pin
or
Ball #
Active
State
SW Initialized HW Reset
Direction
*
PU State Direction
*
PU
or
PD
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