OVERVIEW: Digital Section
1.6.5 ZEUS Digital Signal Processor
The Zeus digital signal processor contains the DSP Engine SC140e:
The following is a list of SC140e features that make this core ideal for a single core modem:
• StarCore™ SC1000 architecture foundation
• 16-Kbyte instructions and 32-Kbyte Data Level 1 caches
• Supervisor- and user-mode task protection
• Memory Management Unit (MMU) tailored to real-time applications
• Compiled C code density on par with the MCU’s
• Branch penalty-minimization with a short, five-stage pipeline
• Low interrupt latency
• Four arithmetic-logic unit (ALU) architecture
• 4-Gbyte linear address range support.
1.6.6 DSP Phase Locked Loop (PLL)
The DSP PLL is programmable and is used to generate a DSP internal clock that is
synchronized to the 16.8 MHz reference frequency. In low power mode, the DSP PLL is
disabled and the DSP operates directly from the 16.8 MHz clock. The DSP PLL runs at
208 MHz.
1.6.7 Serial Peripheral Interface (SPI)
This interface communicates with RF chips using the SPI bus. This bus includes the
following:
• Master Out Slave In (MOSI)
• Master In Slave Out (MISO)
• SPI clock
• Specific chip-select lines
The MCU then sends data to the chip using MOSI and the SPI clock. The MCU also can
receive data from all chips by clocking it into MISO using the SPI clock and appropriate
chip select.
Table 1-2 shows a diagram of the Chip-Select Line States.
Table 1-2. Chip-Select Line States
IC Chip-Select Line Active State
ROADRUNNER Chip Enable SPI CS0 Low
SLEDGEHAMMER Chip Enable SPI CS6 Low
ROADRUNNER primary Chip Enable SPI CS7 Low
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