AMI
®
BIOS Setup
3-11
Advanced Chipset Features
!Note: Change these settings only if you are familiar with the chipset.
Configure SDRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EPROM on the DRAM module. Setting to Enabled enables DRAM
Frequency and SDRAM CAS Latency automatically to be determined by
BIOS based on the configurations on the SPD. Selecting Disabled allows
users to configure these fields manually. The default value is Enabled.
SDRAM CAS Latency
This controls the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it. Settings are 2 and 3. 2 increases the system
performance while 3 provides more stable performance. The default value is
3.
DRAM Frequency
Use this item to configure the clock frequency of the installed DRAMs.
Settings are:
AMIBIOS SETUP - CHIPSET FEATURES SETUP
(C)2001 American Megatrends, Inc. All Rights Reserved
ESC : Quit ↑↓←→ : Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Load Previous Values
F6 : Load Fail-Safe Defaults
F7 : Load Optimized Defaults
Configure SDRAM Timing by SPD:Enabled
SDRAM CAS Latency :3
DRAM Frequency :HCLK-33
DRAM Bank Interleave :Enabled
System Performance :Normal
Memory Hole :Disabled
AGP Mode :Auto
AGP Read Synchronization :Enabled
AGP Fast Write :Disabled
AGP Comp. Driving :Auto
Manual AGP Comp. Driving :CB
AGP Aperture Size :64MB
AGP Master 1 W/S Write :Disabled
AGP Master 1 W/S Read :Disabled
Search for MDA Resources :Yes
PCI Delay Transaction :Enabled
ISA Bus Clock :PCICLK/4
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