Chapter 3
3-14
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. Settings are Enabled (default) and Disabled.
ISA Bus Clock
This item controls the number of clock frequency or timing for ISA bus. The
system divides your PCI clock down to determine the ISA bus clock. For
example, if you select PCICLK/4 (divide-by-4) in the field, because 33MHz
(PCI clock) divided by 4 equals 8.25MHz, the ISA bus clock is 8.25MHz.
Settings are PCICLK/2, PCICLK/3, PCICLK/4, PCICLK/5 and PCICLK/6.
The default value is PCICLK/4.
To Next Page
Loading...
