NAD L75 - Page 15

2-16
Coefficient
Program RAM
SDBCK1
SDWCK1
SDOB0
SDOB1
SDOB2
SDOB3
OVFB RAMA 0~16 RAMA 0~7 SDIB3 SDIB2 SDIB1 SDIB0 SDOA2 RAMOEN RAMWEN RAMCEN SDOA1 SDOA0 CPO XO XI
SDOB Interface
SDOBCKSELSDOBCKSELSDOACKSEL
L,R
/SDBCK0
SDBCK0
SDWCK0
SDIA0
SDIA1
SURENC
KARAOKE
MUTE
CRC
AC3DATA
DTSDATA
NONPCM
LS,RS
C, LFE
SDIBSEL
SDIB Interface
SDOA Interface
SDIA Interface SDIA Interface
ERAMUSE
24 * 16
Sub DSP
SDIASEL
24 * 16
Main DSP
AC-3/Pro Logic/DTS
decoder
Input Buffer
Microprocessor
Interface
Control Registers
IPORT 0~7
/CS
SO
SI
SCK
OPORT 0~7
/CSB
SCK
SI
Control SignalsControl Signals
Data RAM
Delay RAM
PLL
Operating clock
(30MHz)
STREAM 0~7
External RAM
interface
YSS912C BLOCK DIAGRAM
NJU3713G (EXPANDOR IC 84)
Shift Circuit
Latch Circuit
Controller Circuit
P1
P2
P3
P4
P5
P11
P12
CLK
DATA
10
11
12
13
14
15
16
17
1
8
9
STB
CLR