National Instruments PCIe-6323 - Buffered Pulse Train Generation; Finite Implicit Buffered Pulse Train Generation

© National Instruments | 7-31
X Series User Manual
The counter can begin the pulse train generation as soon as the counter is armed, or in response
to a hardware Start Trigger. You can route the Start Trigger to the Gate input of the counter.
You can also use the Gate input of the counter as a Pause Trigger (if it is not used as a Start
Trigger). The counter pauses pulse generation when the Pause Trigger is active.
Figure 7-33 shows a continuous pulse train generation (using the rising edge of Source).
Figure 7-33. Continuous Pulse Train Generation
Continuous pulse train generation is sometimes called frequency division. If the high and low
pulse widths of the output signal are M and N periods, then the frequency of the Counter n
Internal Output signal is equal to the frequency of the Source input divided by M + N.
For information about connecting counter signals, refer to the
Default Counter/Timer Pins
section.
Buffered Pulse Train Generation
X Series counters can use the FIFO to perform a buffered pulse train generation. Buffered pulse
train generation can use implicit timing or sample clock timing. When using implicit timing, the
pulse idle time and active time changes with each sample you write. With sample clocked
timing, each sample you write updates the idle time and active time of your generation on each
sample clock edge. Idle time and active time can also be defined in terms of frequency and duty
cycle or idle ticks and active ticks.
Note On buffered implicit pulse trains, the pulse specifications in the DAQmx
Create Counter Output Channel are ignored so that you generate the number of pulses
defined in the multipoint write. On buffered sample clock pulse trains, the pulse
specifications in the DAQmx Create Counter Output Channel are generated after the
counters start, and before the first sample clock, so that you generate the number of
updates defined in the multipoint write.
Finite Implicit Buffered Pulse Train Generation
Finite implicit buffered pulse train generation creates a predetermined number of pulses with
variable idle and active times. Each point you write generates a single pulse. The number of pairs
of idle and active times (pulse specifications) you write determines the number of pulses
generated. All points are generated back to back to create a user defined pulse train.
SOURCE
OUT
Counter Armed