Page 4 of 9 — DN-6856 • 03/08/04
Network Diagram
TOP, LEFT to RIGHT: J8 Zone Code Input; TB7 DC Power (24 VDC power-limited, both resettable and non-resettable available); TB8 Alarm
Relay; TB9 Trouble Relay; TB10 Supervisory Relay; TB11 Security Relay; SW1, SW5 Relay Switches; JP13 General Board Earth Fault
Jumper; TB12 EIA-485 Terminal Mode (supervised); TB13 EIA-485 ACS Mode (supervised); TB14 EIA-232 Printer; TB15 EIA-232 PC Termi-
nal; J1 NUP (network/service connection: power-limited, supervised); TB16 SLC #1 Connections (detectors, modules; supervised); D55 Main
SLC Ground Fault LED; JP7 Charger Disable Jumper; JP12 200MA Jumper; JP6 Earth Fault Jumper (SLC #1).
LEFT SIDE, TOP to BOTTOM: TB6 NAC #1, TB5 NAC #2, TB4 NAC #3, TB3 NAC #4 (all NAC circuits power-limited and supervised, and each
NAC TB has an NAC LED to the right of it); J7 Accessory Power; Disable/Enable Switches for Degraded Mode; TB2 AC Power Connection;
TB1 Battery Connection (overcurrent protected). BOTTOM, LEFT to RIGHT: D54 AC On LED; System Status Indicator LEDs for “No-
Keyboard Operation”; System Switches SW2 (Acknowledge), SW3 (Silence), SW4 (Reset) for “No-Keyboard Operation”; J4 KDM-2 Connector;
J5, J6 Panel Circuits (ONYX™ Panel Output Modules, supervised); D72 General Board Ground Fault LED; J10 Security Tamper Switch; J11
Auxiliary Trouble Input; D82 AC Power LED; J3 LEM-320 Connector (SLC Loop #2).
6856cpu.wmf
The CPU-640
shown with
KDM-2 Display
6856conf.wmf
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