Nvidia Jetson Orin Nano Series - Page 66

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PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 55
Parameter
Requirement
Units
Notes
Breakout on the same layer as main
Max via stub length
0.4
mm
long via stub requires review (IL and
resonance dip check)
Topology
The main route via dimensions should comply with the via structure rules (See via
section)
See topology in Figure 9-7
For the connector pin vias, follow the rules for the connector pin vias (See via section)
The traces after main route via should be routed as 100 as uncoupled
50ohm SE traces on PCB top or bottom.
Max distance from RPD to main trace (seg B)
1
mm
Max distance from AC cap to RPD stubbing
point (seg A)
~0
mm
Max distance between ESD and signal via
3
mm
Add-on Components
Example of a case where space is limited for
placing components.
AC Cap
Value
0.1
uF
Max via distance from BGA
7.62 (52.5)
mm (ps)
Location
must be placed before pull-down
resistor
The distance between the AC cap and the
HDMI connector is not restricted.
Placement
PTH design
Micro-via design
Place cap on bottom layer if main route
above core
Place cap on top layer if main route
below core
Not Restricted
Void
GND (or PWR) void under/above the
cap is needed. Void size = SMT area +
1x dielectric height keepout distance
Pull-down Resistor (RPD), choke/FET
Value
500
Location.
Must be placed after AC cap
Placement:
Layer of placement
Same layer as AC cap. The FET and
choke can be placed on the opposite
layer thru a PTH via