Nvidia Jetson Orin Nano Series - Test Points for High-Speed Interfaces; Figure 17-3. Serpentine

General Routing Guidelines
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 85
Figure 17-3. Serpentine
17.6 Test Points for High-Speed Interfaces
Ideally, test points are not preferred on very high-speed interface traces as they can degrade
signal integrity. However, to be able to do compliance testing, or interface tuning where
applicable, it may be necessary to include test points at least for early revisions of a design.
The test points are generally required near the receiver. If a connector or some other device
(capacitor, resistor, and so on) exists near the receiver, the pins can be used as test points
without creating additional signal degradation. Where connector or discrete device pins are
not accessible near the receiver end of an interface, it may be necessary to include test points.
When test points are needed for very high-speed interface signals, follow these
recommendations:
 Test points should be very small (less than 0.5 mm).
 Test points should be located on the existing trace (no stub).
 If the test points are placed on differential signals, they should be symmetric for each P
and N signal.