Oki PACEMARK 4410 - Page 207

40496501TH Rev.1 207
Figure B-2-1 Block Diagram
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*
*
+
+
23:;


<
OCS
P1P2P0
P3
TD
RD
IF WR
LS245
2764
ROM
8 KB
RD
TD
RAM
8 KB
Driver
+5 VD
+12V
-12V
+5 V
+9 V
–9 V
+5V
0V
±9 V power
supply circuit
Serial data
control line
Bus line
Control line
"#$
*
*
+
+
,
,
2
2
3
3
4
4
:;<
ADR latch
Receiver
DB0 to DB9
ADR/data bus
ADR bus
80C51
RST
CN1