Appendices
A-42
CJ-series EtherNet/IP Units Operation Manual for NJ-series CPU Unit (W495)
The device variables that correspond to bits 00 to 15 in words x to x+15 are given in the following
table.
I/O memory location in CJ-
series CPU Unit
Device variable for the CJ-series Unit in NJ-series CPU Unit
Word address Bit number Variable name Description
Word x 0 *_x.RegTargetSta.Target-
Sta[0]
Registered Target Node Table Bit for Node
Address 0
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.
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.
.
15 *_x.RegTargetSta.Target-
Sta[15]
Registered Target Node Table Bit for Node
Address 15
Word x+1 0 *_x.RegTargetSta.Target-
Sta[16]
Registered Target Node Table Bit for Node
Address 16
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.
.
.
.
.
15 *_x.RegTargetSta.Target-
Sta[31]
Registered Target Node Table Bit for Node
Address 31
Word x+2 0 *_x.RegTargetSta.Target-
Sta[32]
Registered Target Node Table Bit for Node
Address 32
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.
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.
.
.
.
.
.
15 *_x.RegTargetSta.Target-
Sta[47]
Registered Target Node Table Bit for Node
Address 47
Word x+3 0 *_x.RegTargetSta.Target-
Sta[48]
Registered Target Node Table Bit for Node
Address 48
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.
.
.
.
15 *_x.RegTargetSta.Target-
Sta[63]
Registered Target Node Table Bit for Node
Address 63
Word x+4 0 *_x.RegTargetSta.Target-
Sta[64]
Registered Target Node Table Bit for Node
Address 64
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15 *_x.RegTargetSta.Target-
Sta[79]
Registered Target Node Table Bit for Node
Address 79
Word x+5 0 *_x.RegTargetSta.Target-
Sta[80]
Registered Target Node Table Bit for Node
Address 80
.
.
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.
.
15 *_x.RegTargetSta.Target-
Sta[95]
Registered Target Node Table Bit for Node
Address 95
Word x+6 0 *_x.RegTargetSta.Target-
Sta[96]
Reg
istered Target Node Table Bit for Node
Address 96
.
.
.
.
.
.
.
.
.
15 *_x.RegTargetSta.Target-
Sta[111]
Registered Target Node Table Bit for Node
Address 111