Onkyo HT-R520 Service Manual

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-20
Q800: AK4588VQ (2/8-Channel Audio CODEC with DIR)-4
TERMINAL DESCRIPTION
TX-SR502/E/8250/HT-R520
No. Pin Name I/O Function
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
AVDD
AVSS
RX0
NC
RX1
TEST1
RX2
NC
RX3
PVSS
R
PVDD
RX4
TEST2
RX5
CAD0
RX6
CAD1
RX7
I2C
DAUX2
VIN
MCLK
TX0
TX1
INT0
-
-
I
-
I
I
I
-
I
-
-
-
I
I
I
I
I
I
I
I
I
I
I
O
O
O
Analog Power Supply Pin, 4.5V~5.5V
Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
No Connect
This pin should be connected to PVSS.
Receiver Channel 1 Pin (Internal biased pin)
Test 1 Pin
This pin should be connected to PVSS.
Receiver Channel 2 Pin (Internal biased pin)
No Connect
This pin should be connected to PVSS.
Receiver Channel 3 Pin (Internal biased pin)
PLL Ground pin
External Resistor Pin
12k +/-1% resistor should be connected to PVSS externally.
PLL Power supply pin, 5.0V
Receiver Channel 4 Pin (Internal biased pin)
Test 2 Pin
This pin should be connected to PVSS.
Receiver Channel 5 Pin (Internal biased pin)
Chip Address 0 Pin (ADC/DAC part)
Receiver Channel 6 Pin (Internal biased pin)
Chip Address 1 Pin (ADC/DAC part)
Receiver Channel 7 Pin (Internal biased pin)
Control Mode Select Pin.
"L": 4-wire Serial, "H": I
2
C Bus
Auxiliary Audio Data Input Pin (DIR/DIT part)
V-bit Input Pin for Transmitter Output
Master Clock Input Pin
Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When TX bit = "0", Transmit Channel (Through Data) Output 1 Pin.
When TX bit = "1", Transmit Channel (DAUX2 Data) Output Pin (Default).
Interrupt 0 Pin

Onkyo HT-R520 Specifications

General

Brand	Onkyo
Model	HT-R520
Category	Receiver
Language	English