Panasonic FP2

FP2 Serial Data Unit
Sample Programs
8 − 8
8.1 Sample Programs
( RET )
, K0 , K251 , I0K0 , DT100
F150 READ
,DT50 ,K2
F27 —
,DT53
R9010
, K 2 , DT 100
F70 BCC
, DT 53 , DT 54
,DT54 ,K1
F71 HEXA
,DT55
,DT50 ,K2
F27 —
,DT56
R9010
,DT56 ,K2
F32 %
,DT57
,DT57 ,I0
F0 MV
,I0DT100 , DT 60
F1 DMV
,DT50 ,K2
F32 %
,DT58
R9010
, DT90015 , K 1
F60 CMP
R900B R100
, DT 60 , DT61
F112 WBSR
R100
, DT 60 , DT61
F112 WBSR
R9010
, DT 60 , DT 55
F60 CMP
S
R101
S
R102
R900B
R900B
Data indicating number of received
words is read from address 251 of the
shared memory (received buffer of
CH1).
Block check code is calculated.
− Number of bytes received is calcu-
lated (not including BCC).
− Block check code is calculated.
− Result is converted from HEX to
hexadecimal ASCII code.
BCC segment is extracted from re-
ceived data.
Number of received data bytes is
judged to be even or odd.
Number of received data bytes is
odd.
If odd, data is shifted one byte to
the right.
BCC is judged as OK or NG.
BCC OK
BCC NG
is read to the data register DT100.
Specifies the FP2 serial data unit in
slot no.0.
The contents of the word indicated by
I0 of the shared memory address 251