Philips CD-I - Page 98

4) Interrupt register bit assignment of NCR5380
CPU68070 D15 D14 Dl3 D12 Dll DlO D09 DOB
NCR5380
D07 D06 DOS D04 D03 D02 DOl DOO
5) Interrupt handling to CPU68070
The
external interrupt register 4 in the system
control register of the CPU68070 should be set
before the interrupt os asserted. For the
interruption, INTEX4- an dIACKEX4- signal are
used.
1.7.3 DMA controller
1) Clock frequency
10.0 Mhz
2)
Channel
channel 1 SCSI interface
channel 2 not used
channel 3 not used
channel
4
not used
3) Internal registers of DMA controller
channel 1:
Address Register Length Note
--------------------------------------------------
400000 CSR Byte channel status register
400001 CER
Byte channel error register
400004 DCR Byte device control register
400005 OCR Byte operation control register
400006
SCR Byte sequence control register
400007 CCR Byte channel control register
40000A
MTC
Word memory transfer counter
400014 MAR 1 Word memory address register
40001A DAR 1 Word device address register
40001C BTC Word
base transfer counter
400025 BAR 1 Word base address register
400027 NIV Byte normal interrupt vector
40002D CPR Byte
channel priority register
400029 MFC Byte memory function code
400031 DFC Byte device function code
400039 BFC Byte base function code
4000FF GCR Byte general
control register
7-18
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