PSI DRS4 - Page 24

DRS4 Evaluation Board User’s Manual
Page 24 of 43
The binary format requires less space and can be written faster, but it requires a special
program to read and analyze the data afterwards.
Depending on the number of channels that are “on” during data acquisition, the file contains
up to four channels for each evaluation board, which can be identified by their channel
headers. In a multi-board setup (starting with software version 4.1) there can be more than
one board per event. In this case there are several board blocks with different board serial
numbers.
At the beginning of each file there is a section that contains the timing calibration of one or
more boards. In the DRS4 chip, the “width” of each sampling bin is different, and therefore
needs to be measured and calibrated. This timing calibration is stored inside the EEPROM of
each evaluation board. The timing section at the beginning of the binary file contains a copy
of this timing calibration. Since it is constant over time, it is valid for all events in the file and
is not repeated for each event in order to save space. Starting with the V5 board, each channel
has its own calibration. Depending which channels were turned on during acquisition, there
might be 1-4 timing calibration arrays, which can be seen from the channel headers.
One problem however is that in each event the readout starts at a different position of the
DRS4 chip (the so-called “trigger cell”). Unlike in the XML format, the voltage/time pairs
have to be calculated for each event individually. If the array dt
ch
[1024] contains the effective
bin widths of a channel ch of the DRS4 chip obtained from the binary file, the time t
ch
[i]
belonging to sample i can be calculated using the trigger cell tcell as follows:
t
ch
[i] = dt
ch
[( j + tcell)%1024]
j=0
i−1
∑
where % is the modulo operator. The time array starts with t
ch
[0]=0.
Another complication comes from the fact that the timing of the channels in a DRS chip is
different. So a given cell i has a different absolute time in each channel. The only common
point in time is cell #0 (the first cell in the capacitor array), which has the same absolute time
in all DRS channels. To obtain best timing, it is therefore necessary to align all channels such
that their cell #0 has the same time t
ch,0
as given by
t
ch,0
= t
ch
[(1024 − tcell)%1024]
If channel 1 is used as the reference point, the time arrays of the other channels can be shifted
so that their cell #0 aligns:
t
ch
[i]
corrected
= t
ch
[i] − (t
ch,0
− t
0,0
)
The distribution contains a file read_binary.cpp, which reads the binary data format produced
by DRSOsc and calculates the correct times as described above. It can be used as an example
program to analyze binary waveform data.
The timing calibration section is followed by the actual waveform data. Each event can be
identified by the event header ‘EHDR’, which is followed by one or more arrays of sampling
values, depending on what channel was enabled during the acquisition. The voltage values are
encoded as 2-byte integers, were 0 corresponds to -0.5V and 65535 corresponds to +0.5V.
All multi-byte data is encoded with LSB first, as in all Intel PC systems.