DRS4 Evaluation Board User’s Manual
Page 29 of 43
@ 5V). The linear regulator of the evaluation board V2 could however not be used, since the
efficiency would be too low. Instead, a switching regulator LMZ10503 from National
Semiconductor
®
is used on the board. It has an efficiency of more than 95% and a low output
ripple. The output voltage of 3.3V is then converted using traditional linear regulators into
two 2.5V low noise power supplies, which power the analog part of the board.
Other designs are possible which push the analog bandwidth to 800 or 900 MHz, close to the
theoretical limit of 950 MHz of the DRS4 chip, but they require more power.
The usual design rules like proper termination, matched impedance PCB traces and separate
power supply PCB planes apply as in any high frequency analog design.
4.3. Control Voltages
The DRS4 chip requires certain control voltages: ROFS, O-OFS and BIAS. The latter two are
generated internally with some default voltage, but can be “overwritten” by an external low
impedance source. It is recommended to connect these lines to an external 16-bit DAC, so
that the DRS4 input range can be fine-tuned on a board-by-board basis, to compensate for
chip variations. The ROFS signal should be driven by a high speed low noise buffer. If this
signal would be directly connected to the DAC output, the signal height would change
slightly during the chip readout and the measurement would show a varying baseline level.
4.4. ADC Clock
There is a very strict relation between the DRS4 output shift register clock SRCLK and the
ADC clock (see DRS4 data sheet WAVEFORM READOUT). In order to reduce the noise
due to aperture jitter, the phase shift between these two clocks must be fixed and contain very
small jitter (~10ps). The easiest way to generate this phase shift is to use the digital clock
managers (DCM) in the FPGA, as it is done on the evaluation board. Since the DCMs have
however an inherent phase jitter of up to 150ps, this introduces some noise in form of a
baseline variation when sampling a DC signal in the order of up to a few mV. If this becomes
a problem, it is recommended to generate the phase shift between these two clocks with a low
jitter delay circuit.
4.5. Calibration
In order to perform a proper voltage calibration of the DRS4 chip, a well-defined DC voltage
needs to be connected to all DRS4 inputs and measured. The evaluation board uses the on-
board 16-bit DAC connected to all inputs for that purpose. Since the DRS4 chip draws quite
some current on its inputs, the DAC is buffered via a low noise OpAmp AD8605.
For the timing calibration, a low jitter 100 MHz sine wave needs to be connected to all
channels. In evaluation boards previous to version 5, only one DRS4 channel was connected
to the clock, which allows timing calibrations good for about 10-15 ps. To achieve the
ultimate resolution below 3 ps, the clock needs to be connected to all DRS4 channels via
analog switches. The sine wave is obtained from a low jitter quartz oscillator with a passive
3
rd
order low pass filter. Since the oscillator would cause some noise during normal operation,
it can be disabled through the FPGA.
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