DRS4 Evaluation Board User’s Manual
Page 7 of 43
1.3. Firmware Description
Both the Windows and the Linux distribution contain a subdirectory “firmware” which
contains the FPGA and Microcontroller firmware for the DRS4 Evaluation Board. The FPGA
firmware is written in pure VHDL, thus making it easy to port it to other FPGA devices such
as Altera
®
or Lattice
®
. Only a few Xilinx
®
basic components such as clock managers and I/O
blocks have been instantiated and must be adapted when another FPGA manufacturer than
Xilinx
®
is chosen. The FPGA source code is contained in several files with following
contents:
Top level entity. Routing of clock signals, global reset signal,
LEDs and LEMO input
Main file containing state machines for DRS4 readout, serial
interface to DAC, EEPROM and temperature sensor, trigger
logic and reference clock generation
Instantiates block ram for waveform storage
Interface to CY2C68013A microcontroller in slave FIFO mode.
Implements a set of status and control registers through which
the main application can be controlled
Generates 66 MHz, 132 MHz, 264 MHz and a phase shifted 66
MHz clock out of the 33 MHz quartz input frequency via the
Xilinx
®
Digital Clock Managers (DCM)
Constraint file. Assigns package pins and defines clock
constraints
Xilinx
®
ISE 9.2i project file
Compiled firmware image directly for Spartan 3s400 FPGA
Compiled firmware image for FPGA EEPROM XCF02S
Xilinx
®
Impact project file to program FPGA via download
cable
The firmware for the USB microcontroller from Cypress
®
is written in C and must be
compiled with the Keil
®
8051 C compiler. It contains the standard include and library files
from the Cypress EZ-USB
®
development kit plus some DRS specific files:
Main micro controller firmware file
Compiled firmware file (Intel HEX format)
Compiled firmware file (For Cypress EZ-USB Console
download)
Remaining files are standard files from EZ-USB development
kit