LPWA  Module  Series 
   BG96  Hardware  Design 
 
BG96_Hardware_Design                                                    28 / 79 
 
 
 
  Driving the host DTR to low level will wake up the module.   
  When BG96 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for 
details about RI behavior. 
  AP_READY will  detect  the  sleep  state of  the  host  (can  be  configured  to  high  level  or  low  level 
detection). Please refer to AT+QCFG=“apready” command in document [2] for details. 
 
3.5. Power Supply 
3.5.1.  Power Supply Pins 
BG96 provides the following four VBAT pins for connection with an external power supply. There are two 
separate voltage domains for VBAT.   
 
  Two VBAT_RF pins for module’s RF part. 
  Two VBAT_BB pins for module’s baseband part. 
 
The following table shows the details of VBAT pins and ground pins. 
 
Table 6: VBAT and GND Pins 
 
3.5.2.  Decrease Voltage Drop 
The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will 
never drop below 3.3V. The  following figure shows the voltage drop during burst transmission in  2G 
network. The voltage drop will be less in LTE Cat M1 and LTE Cat NB1 networks.   
 
 
Power supply for the 
module’s RF part 
Power supply for the 
module’s baseband part 
3, 31, 48, 50, 54, 
55, 58, 59, 61, 62, 
67~74, 79~82, 
89~91, 100~102