Quectel BG96 - Page 40

LPWA Module Series
BG96 Hardware Design
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Table 12: Pin Definition of UART2 Interface
Table 13: Pin Definition of UART3 Interface
The logic levels are described in the following table.
Table 14: Logic Levels of Digital I/O
The module provides 1.8V UART interface. A voltage-level translator should be used if customers’
application is equipped with a 3.3V UART interface. The voltage-level translator TXS0108EPWR provided
by Texas Instruments is recommended. The following figure shows a reference design.
Pin Name
Pin No.
I/O
Description
Comment
DBG_RXD
22
DI
Receive data
1.8V power domain
DBG_TXD
23
DO
Transmit data
1.8V power domain
Pin Name
Pin No.
I/O
Description
Comment
UART3_TXD
27
DO
Transmit data
1.8V power domain
UART3_RXD
28
DI
Receive data
1.8V power domain
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0
0.45
V
V
OH
1.35
1.8
V