Quectel SG368Z-AP - Page 73

Smart Module Series
SG368Z_Series_Hardware_Design 72 / 113
Figure 24: Schematic Diagram of PCIe1 Interface
Module
PCIe 3.0 Clock IC
EP
× 2 Lane RC
× 2 Lane EP
Figure 25: Schematic Diagram of 2 Lane RC Mode of PCIe2 Interface
Module
RC
× 2 Lane EP
× 2 Lane RC
PCIe 3.0 REFCLK
Figure 26: Schematic Diagram of 2 Lane EP Mode of PCIe2 Interface
Module
PCIe 3.0 Clock IC
× 1 Lane RC
× 1 Lane EP
× 1 Lane EP
× 1 Lane RC