Smart Module Series
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Figure 27: Schematic Diagram of 1 Lane RC + 1 Lane RC Mode of PCIe2 Interface
1. 100 nF AC coupling capacitors are connected in series on the PCIe 2.0 data traces, and 220 nF AC
coupling capacitors are connected in series on the PCIe 3.0 data traces.
2. When PCIe2 uses × 2 lane mode or × 1 lane mode, control signals are PCIE2_CLKREQ0_N,
PCIE2_WAKE0_N and PCIE2_RST0_N.
3. When PCIe2 uses × 1 lane mode + × 1 lane mode, channel 0 control signals are
PCIE2_CLKREQ0_N, PCIE2_WAKE0_N and PCIE2_RST0_N; channel 1 control signals are
PCIE2_CLKREQ1_N, PCIE2_WAKE1_N and PCIE2_RST1_N.
4. The impedance of the PCIe 2.0 data traces is controlled to 90 Ω, and the impedance of the PCIe 3.0
data traces is controlled to 85 Ω.
5. The impedance of the PCIe reference clock traces is controlled to 100 Ω.
6. For detailed signal connection, refer to document [3].
To ensure performance, the following principles should be complied with when designing PCIe interfaces:
⚫ PCIe are high-speed signal traces, supporting maximum data rate up to 2.5 Gbps for PCIe 2.0 and
the differential impedance should be controlled to 90 Ω. The maximum data rate is up to 4 Gbps for
PCIe 3.0 and the differential impedance should be controlled to 85 Ω. Additionally, it is recommended
to route the traces on the inner layer of PCB and do not cross it with other traces. To avoid crosstalk,
a clearance of 4 times the trace width among PCIe 2.0 signal traces and a clearance of 5 times the
trace width among PCIe 3.0 signal traces are recommended. During impedance matching, do not
connect PCIe signal traces to GND on different planes to ensure impedance consistency.
⚫ Route PCIe traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance of data traces and reference clock traces according to
requirements and the deviation is at most 10 %;
c) Control intra-lane length matching within 0.3 mm.
Table 31: PCIe Interface Trace Length Inside the Module (Unit: mm)
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