Quectel SG368Z Series

Smart Module Series
SG368Z_Series_Hardware_Design 27 / 113
RGMII0_TX_CLK
163
DO
RGMII0 transmit
clock
VCCIO4
Only SG368Z-AP
supports this pin.
RGMII0_MDC
181
DO
RGMII0
management data
clock
VCCIO4
Only SG368Z-AP
supports this pin.
RGMII0_MDIO
185
OD
RGMII0
management data
input/output
VCCIO4
Only SG368Z-AP
supports this pin.
RGMII0_
REFCLKOUT
160
DO
RGMII0 reference
clock output
VCCIO4
The output
frequency of
reference clock is
25 MHz.
RGMII0_MCLK
177
DI
RGMII0 clock input
VCCIO4
The output
frequency of
reference clock is
125 MHz;
Only SG368Z-AP
supports this pin.
RGMII1_RX0
296
DI
RGMII1 receive data
bit 0
VCCIO6
RGMII1_RX1
294
DI
RGMII1 receive data
bit 1
VCCIO6
RGMII1_RX2
308
DI
RGMII1 receive data
bit 2
VCCIO6
RGMII1_RX3
307
DI
RGMII1 receive data
bit 3
VCCIO6
RGMII1_RX_CTL
293
DI
RGMII1 receive
control
VCCIO6
RGMII1_RX_CLK
304
DI
RGMII1 receive
clock
VCCIO6
RGMII1_TX0
305
DO
RGMII1 transmit
data bit 0
VCCIO6
RGMII1_TX1
303
DO
RGMII1 transmit
data bit 1
VCCIO6
RGMII1_TX2
312
DO
RGMII1 transmit
data bit 2
VCCIO6
RGMII1_TX3
310
DO
RGMII1 transmit
data bit 3
VCCIO6
RGMII1_TX_CTL
298
DO
RGMII1 transmit
control
VCCIO6
RGMII1_TX_CLK
306
DO
RGMII1 transmit
clock
VCCIO6
RGMII1_MDC
290
DO
RGMII1
management data
VCCIO6