Quectel SG368Z Series

Smart Module Series
SG368Z_Series_Hardware_Design 75 / 113
Table 32: Pins Description of RGMII Interfaces
Pin Name
Pin No.
I/O
Description
Comment
RGMII0_RX0
183
DI
RGMII0 receive data bit 0
Only SG368Z-AP supports
this pin.
RGMII0_RX1
179
DI
RGMII0 receive data bit 1
RGMII0_RX2
174
DI
RGMII0 receive data bit 2
Only SG368Z-AP supports
this pin.
RGMII0_RX3
169
DI
RGMII0 receive data bit 3
Only SG368Z-AP supports
this pin.
RGMII0_RX_CTL
175
DI
RGMII0 receive control
RGMII0_RX_CLK
164
DI
RGMII0 receive clock
Only SG368Z-AP supports
this pin.
RGMII0_TX0
168
DO
RGMII0 transmit data bit 0
Only SG368Z-AP supports
this pin.
RGMII0_TX1
173
DO
RGMII0 transmit data bit 1
Only SG368Z-AP supports
this pin.
RGMII0_TX2
178
DO
RGMII0 transmit data bit 2
Only SG368Z-AP supports
this pin.
RGMII0_TX3
182
DO
RGMII0 transmit data bit 3
Only SG368Z-AP supports
this pin.
RGMII0_TX_CTL
172
DO
RGMII0 transmit control
Only SG368Z-AP supports
this pin.
RGMII0_TX_CLK
163
DO
RGMII0 transmit clock
Only SG368Z-AP supports
this pin.
RGMII0_MDC
181
DO
RGMII0 management data
clock
Only SG368Z-AP supports
this pin.
RGMII0_MDIO
185
OD
RGMII0 management data
input/output
Only SG368Z-AP supports
this pin.
RGMII0_
REFCLKOUT
160
DO
RGMII0 reference clock
output
The output frequency of
reference clock is 25 MHz.
RGMII0_MCLK
177
DI
RGMII0 clock input
The output frequency of
reference clock is 125 MHz;
Only SG368Z-AP supports
this pin.
RGMII1_RX0
296
DI
RGMII1 receive data bit 0
RGMII1_RX1
294
DI
RGMII1 receive data bit 1
RGMII1_RX2
308
DI
RGMII1 receive data bit 2