160 Rabbit 2000 Microprocessor
Figure 15-5 shows the effect of adding an extra wait state to the memory read/write cycles.
The effects are similar for the I/O bus read/write cycles.
Figure 15-5. Memory Read and Write with Wait States
T
adr
T
adr
Memory Read (one wait state)
/WE
T
hold
CLK
A[19:0]
D[7:0]
T
setup
T
hold
Memory Write (one wait state)
CLK
A[19:0]
D[7:0]
/CSx
valid
/OEx
/CSx
valid
/WEx
valid
T1
Tw
T1
Tw
Tw1
T2
valid
valid
T2
valid
To Next Page
Loading...
