Renesas RH850/F1Kx Series - Figure 15: RH850;F1 KH-D8 Power Up;Down Timing

RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 43 of 108
August 8, 2019
b) When
RESET terminal is not used
Figure 15: RH850/F1KH-D8 Power up/down timing
Note: tVS is the timing of the voltage slope
REG0VC C/ EVCC
VP OC (mi n )
A0 VRE F
3.0V
0V
0V
A1VREF
3.0V
0V
BVCC
3.0V
0V
Min. 0 us
Max. 500 us
REG1VCC
VP OC( mi n)
0V
Min. 0 us
Max. 1 us
Min. -1 us
Max. 0.5/tVS ms
Min. -1 us
Max. 0.5/tVS ms
Min. -1 us
Max. 0.5/tVS ms
Min. 0 us
Max. 500 us
Min. 0 us
Max. 500 us
Min. 0 us
Max. 500 us