Renesas RH850/F1Kx Series - Figure 19: RH850;F1 K Power Up;Down Timing; Figure 20: RH850;F1 K Power Up;Down Timing

RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 52 of 108
August 8, 2019
c) When
RESET terminal is used
Figure 19: RH850/F1K Power up/down timing
d) When
RESET terminal is not used
Figure 20: RH850/F1K Power up/down timing
Note: For the spec of t
DPOR
, t
DRPD
and t
VS
, please refer to the Section 40.8.2 Power Up/Down Timing of the
RH850/F1K Hardware User’s Manual.
REGVCC/EVCC
VPOC(min)
0V
RESET
0V
VIL
A0VREF
3.0V
0V
A1VREF
3.0V
0V
Min. 0 us
Min. 0 us
Min. 0 us
Min. 0 us
t
DP OR
Max . 0.5/tVS ms
Min. 0 us
Max . 0.5/tVS ms
Min. 0 us
t
DRP D
REGVCC/EVCC
VP OC (min)
0V
A0VREF
3.0V
0V
A1VREF
3.0V
0V
Min. 0 us
Max . 500 us
Min. 0 us
Max . 500 us
Min. -1 us
Max . 0.5/tVS ms
Min. -1 us
Max . 0.5/tVS ms