Sanyo PLC-XF71 - Page 144

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Control Port Functions
PIN NO. NAME FUNCTION NAME FUNCTION POLARITY I /O
69 A6 SH_A6 Adress bus O
70 A7 SH_A7 Adress bus O
71 A8 SH_A8 Adress bus O
72 A9 SH_A9 Adress bus O
73 A10 SH_A10 Adress bus O
74 A11 SH_A11 Adress bus O
75 VssQ GND
76 A12 SH_A12 Adress bus O
77 VccQ 3.3V
78 A13 SH_A13 Adress bus O
79 A14 SH_A14 Adress bus O
80 A15 SH_A15 Adress bus O
81 A16 SH_A16 Adress bus O
82 A17 SH_A17 Adress bus O
83 A18 SH_A18 Adress bus O
84 A19 SH_A19 Adress bus O
85 A20 SH_A20 Adress bus O
86 VssQ GND
87 A21 SH_A21 Adress bus O
88 VccQ 3.3V
89 A22 SH_A22 Adress bus O
90 A23 SH_A23 Adress bus O
91 Vss GND
92 A24 SH_A24 Adress bus O
93 Vcc 1.9V
94 A25 SH_A25 Adress bus O
95 BS / PTK[4] BS [ICE] Bus Cycle Start Signal O
96 RD RD O
97 WE0 / DQMLL WE0 D7 - D0 Select Signal / DQM (SDRAM) O
98 WE1 / DQMLU / WE WE1 D15 - D8 Select Signal / DQM (SDRAM) O
99 WE2 / DQMUL / ICIORD / PTK[6] WE2 D23 - D16 Select Signal / DQM (SDRAM) O
100 VssQ GND
101 WE3 / DQMUU / ICIOWR / PTK[7] WE3 D31 - D24 Select Signal / DQM (SDRAM) O
102 VccQ 3.3V
103 RD / WR RDWR Read / Write O
104 PTE[7] / PCC0RDY / AUDSYNC AUDSYNC ADU SYNC O
105 CS0 CS0 Chip Select 0 Flash Memory [16bit] O
106 CS2 CS2 Chip Select 2 Divice1 [16bit] O
107 CS3 CS3 Chip Select 3 SDRAM [32bit] O
108 CS4 / PTK[2] CS2 Chip Select 4 Divice2 [16bit] O
109 CS5 / CE1A / PTK[3] not used Chip Select 5 Divice3 [8bit] O
110 CS6 / CE1B not used Chip Select 6 Divice4 [8bit] O
111 CE2A / PTE[4] ON_15V LCD Panel Drive Power Control O
112 CE2B / PTE[5] not used Setting DPRAM O
113 AFE_HC1 / USB1d_DPLS / PTK[0] MOTHR_FPGA_CCLK Clock Pin for Configuration O
114 AFE_RLYCNT / USB1d_DMNS / PTK[1] MOTHR_FPGA_PROG Configuration Start Pin O
115 VssQ GND
116 AFE_SCLK / USB1d_TXDPLS not used AFE CLOCK O
117 VccQ 3.3V
118 PTM [7]/PINT[7]/AFE_FS/USB1d_RCV not used not used I
119 PTM [6]/PINT[6]/AFE_RXIN/USB1d_SPEED not used not used I
120 PTM[5]/PINT[5]/AFE_TXOUT/USB1d_TXSE0 not used not used I
121
PTM [4]/PINT[4]/AFE_RDET/
USB1d_TXDMNS
PW_BSY DPRAM Access Control (Input) "L" : BYSY I
122 RESARVATION / USB1d_SUSPEND not used Resarvation / Transceiver Suspend Output O
123 USB1_ovr_crnt / USBF_VBUS USBF_VBUS [Func] USB Function Bus I
124 USB2_ovr_crnt not used USB Host2 Over_Current Detect I
125 RTS2 / USB1d_TXENL not used SCIF RTS Terminal / USB Output Enable Terminal O
126 PTE[2] / USB1_pwr_en USB_pwr_en [Func] USB1 Voltage Control O
127 PTE[1] / USB2_pwr_en not used USB2 Voltage Control O
128 CKE / PTK[5] CKE CK Enable (SDRAM) O
129 RAS3 / PTJ[0] RAS3 RAS for SDRAM O
130 PTJ[1] SH_EEP_WP EEPROM Write Protect O
131 RESARVATION / CAS / PTJ[0] CAS CAS for SDRAM O
132 VssQ GND
133 PTJ[3] MOTHER_FPGA_DATA Configuration Data Pin O
134 VccQ 3.3V
135 PTJ[4] NIOS_FPGA_CCLK Configuration Clock Pin O
136 PTJ[5] NIOS_FPGA_PROG Configuration Start Pin O
137 Vss GND