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Control Port Functions
PIN NO. NAME FUNCTION NAME FUNCTION POLARITY I /O
138 PTD[5] / CL1 PW_RESET PW Reset Signal O
139 Vcc 1.9V
140 PTD[7] / DON SH_PW_0 SH Reset Software Protect
" L" : E n a b l e
"H" :disable
O
141 PTE[6] / M_DISP NIOS_FPGA_DATA Configuration data Pin O
142 PTE[3] / FLM SF_BSY DPRAM Access Control (Output) "L" : BYSY O
143 PTE[0] / TDO TDO [ICE] Test Data Output O
144 PCC0RESET / DRAK0 not used PCC Reset / DMA Demand receipt O
145 PCC0DRV / DACK0 not used PCC Buffer Control / DMA Acknowlege 0 O
146 WAIT not used Hardware Wait I
147 RESETM RESETM Manual Reset Demand I
148 ADTRG / PTH[5] not used Analog Trigger / Input Port H I
149 IOIS16 / PTG[7] not used IOIS16(PCMCIA) / Input Port G I
150 ASEMD0 ASSEMD0[ICE] ASE Mode I
151 PTG[5] / ASERKAK ASEBRKAK [ICE] ASE Break Acknowlege O
152 PTG[4} not used Input Port G I
153 PCC0BVD2 / PTG[3] / AUDATA[3] AUDATA[3] AUDATA[3] O
154 PCC0BVD1 / PTG[2] / AUDATA[2] AUDATA[2] AUDATA[2] O
155 Vss GND
156 PCC0BCD2 / PTG[1] / AUDATA[1] AUDATA[1] AUDATA[1] O
157 Vcc 1.9V
158 PCC0BCD1 / PTG[0] / AUDATA[0] AUDATA[1] AUDATA[0] O
159 VssQ GND
160 PTF[7] / PINT[15] / TRST TRST Test Reset I
161 VccQ 3.3V
162 PTF[6] / PINT[14] / TRST TMS Test Mode Switch I
163 PTF[5] / PINT[13] / TDI TDI Test Data Input I
164 PTF[4] / PINT[12] / TCK TCK Test Clock I
165 PTF[3] / PINT[11] not used Input Port F / Port Interrupt / Resarvation I / I / O
166 PCCREG / PTF[2] / RESARVATION not used PCC REG / Input Port F / Resarvation O / I / O
167 PCCVS1 / PTF[1] / RESARVATION not used PCC VS1 / Input Port F / Resarvation I / I / O
168 PCCVS2 / PTF[0] / RESARVATION MOTHER_FPGA_NSTATUS Error Detect I
169 MD0 MD0 Setting Clock Mode Always : L O / I / O
170 Vcc_PLL1 1.9V Power PLL1
171 CAP1 CAP1 PLL1 External Capacity Terminal
172 Vss_PLL1 GND
173 Vss_PLL2 GND
174 CAP2 CAP2 PLL2 External Capacity Terminal
175 Vcc_PLL2 1.9V Power PLL1
176 PCC0WAIT / PTH[6] / AUDCK AUDCK AUD Clock I
177 Vss GND
178 Vcc 1.9V
179 XTAL not used Clock Oscilator O
180 EXTAL EXTAL External Clock / Crystal Oscilator [33.33333MHz] I
181 LCD15 / PTM[3] / PINT[10] MOTHER_FPGA_DONE AUD Clock / Configuration Process End Signal I
182 LCD14 / PTM [2] / PINT[9] SH_CHK_DPRAM PW_INT Clear Monitor (Input) "L" : Non Clear I
183 LCD13 / PTM[1] / PINT[8] NIOS_FPGA_NSTATUS Error Detect I
184 LCD12 / PTM[0] NIOS_FPGA_DONE Normary Ends Detect I
185 STATUS0 / PTJ[6] READY_LED Ready LED Output "H" : ON O
186 STATUS1 / PTJ[7] IC_RESET_CPU IC Power Conyrol O
187 CL2 SH_FLASH_WP Flash Write Protect O
188 VssQ GND
189 CKIO CKIO System Clock Input / Output I / O
190 VccQ 3.3V
191 TxD0 / SCPT[0] SH_LB_UART Send Data (Network)
1 9 2 0 0 b p s /
9600bps
O
192 SCK0 / SCPT[1] not used Serial Clock 0 / SCI IO Port IO / IO
193 TxD_SIO / SCPT[2] not used SIOF Send Data / SCI Output Port O / O
194 SIOMCLK / SCPT[3] not used SIOF Clock Input / SCI IO Port I / IO
195 TxD2 / SCPT[4] SH_EX_UART Send Data ( External)
1 9 2 0 0 b p s /
9600bps
O
196 SCK_SIO / SCPT[5] not used SIOFClock / SCI IO Port IO / IO
197 SIOFSYNC / SCPT[6] not used SIOF Flame Sync / SCI Output Port IO / IO
198 RxD0 / SCPT[0] LB_SH_UART Receive Data (Network)
1 9 2 0 0 b p s /
9600bps
I
199 RxD_SIO / SCPT[2] not used SIOF Receive Data / SCI INput Port I / I
200 Vss GND
201 RxD2 / SCPT[4] EX_SH_UART Receive Data (external) 19200bps / 9600bps I
202 Vcc 1.9V
203 SCPT[7] / CTS2 / IRQ5 SH_IRQ_SHUT Shutter Interrupt I / I / I
204 LCD11 / PTC[7] / PINT[3] SH_SDA_Slot4 IIC Bus (Slot4) "L" : Active IO
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