Sharp 27DV-S100 - IC502 IX1765 GE 4 M EDO DRAM Description; 4 M EDO DRAM IC Block Diagram

77
27DV-S100
27DV-CS10
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
ID
Register
DATA
QUEUE
REGISTER
CSR
ESRs
Data
Comparator
DQ
8-14
DQ
0-7
I/O Logic
OUTPUT MULTIPLEXER
Register
Program Erase
Voltage Switch
BYTE#
CUIWSM
16-KBYTE
Block 31
16-KBYTE
Block 30
16-KBYTE
Block 1
16-KBYTE
Block 0
CE#
OE#
WR#
RP#
RY/BY#
V
PP
V
CC
GND
Y GATING/SENSING
Y-DECODER
X-DECODER
Input
Buffer
ADDRESS
QUEUE
LATCHES
ADDRESS
COUNTER
A
-1.0~18
• Block Diagram
• Block Diagram
RAS clock
generator
CAS clock
generator
WE clock
generator
Data I/O Bus
Column decoders
Sense amplifiers
Refresh
counter
Address buffers
and predecoders
Row
decoders
Memory
array
OE clock
generator
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O
Buffer
9
Y
0 -Y 8
X 0 -X 8
512
512 16
OE
WE
UCAS
LCAS
RAS
V
CC
V SS
A0
A1
A7
A8
IC502 IX1765GE 4M EDO DRAM
Terminal Terminal name Function
16-19, 22-26 A0-A8 Address inputs.
14 RAS Row address strobe.
28 UCAS Column address strobe/upper byte control.
29 LCAS Column address strobe/lower byte control.
13 WE Write enable.
27 OE Output enable.
2-5, 7-10 DQ
1-DQ16 Data inputs/outputs.
31-34, 36-39
1, 6, 20 VCC +3.3V power supply.
21, 35, 40 VSS 0V ground.
11-12, 15, 30 NC No connection.