Output Signals
A16 ∼ A23 ∗ High-Order Address Bits.
These are the most significant 8 bits of the memory ad-
dress bus.
HBE ∗ High Byte Enable.
Status signal used to enable data transfers on the most
significant byte of the data bus.
ST0 ∼ 3 Status.
Not used.
U/S User/Supervisor.
Not used.
ILO Interlocked Operation.
Not used.
HLDA Hold Acknowledge.
Activated by the CPU in response to the HOLD input to in-
dicate CPU has released the bus.
PFS Program Flow Status.
A pulse on this signal indicates the beginning of execution
of instruction.
BPU BPU Cycle.
Not used.
RSTO Reset Output.
This signal becomes active when RSTI is low, initiating a
system reset.
RD Read Strobe.
Activated during CPU or DMA read cycles to enable read-
ing of data from memory or peripherals.
WR Write Strobe.
Activated during CPU or DMA write cycles to enable writ-
ing of data to memory or peripherals.
TSO Timing State Output.
Not used.
DBE Data Buffers Enable.
Used to control external data buffers. It is active when the
data buffers are to be enabled.
OSCOUT Crystal Output.
Not used.
IAS SPecial Cycle Address Strobe.
Not used.
CTTL1 – 2 System Clock.
Output clock for bus timing. CTTL1 and CTTL2 must be
externally connected together.
FCLK Fast Clock.
Not used.
ALE Address Latch Enable.
Active high signal that can be used to control external ad-
dress latches.
IOUT Interrupt Output
Not used.
Input-Output Signals
AD0 ∼ 15 * Address/Data Bus.
Multiplexed Address/Data Information. Bit 0 is the least
significant bit of each.
SPC Slave Processor Control.
Not used.
DDIN * Data Direction.
Status signal indicating the direction of the data transfer
during a bus cycle. During HOLD acknowledge this signal
becomes an input and determines the activation of RD or
WR.
ADS * Address Strobe
Controls address latches; signals the beginning of a bus
cycle. During HOLD acknowledge this signal becomes an
input and the CPU monitors it to detect the beginning of
a DMA cycle and generate the relevant strobe signals.
When a DMA is used, ADS should be pulled up to V
CC
through a 10 kΩ resistor.
(3) LC8213K (IC505) Pin Layout
I: Input pin
O: Output pin
B: Bidirectional pin
P: Power pin
NC: Not connected
No. Pin name Type
1 CS I
2 RD I
3WR I
4A2 I
5A1 I
6A0 I
7V
DD
P
8NC
9D7 B
10 D6 B
11 D5 B
12 D4 B
13 V
SS
P
14 D3 B
15 D2 B
16 D1 B
17 D0 B
18 NC
19 NC
20 IREQ O
21 DREQ O
22 DACK I
23 NC
24 NC
25 NC
26 NC
27 RESET I
28 CLK I
29 V
SS
P
30 TEST4 I
31 V
DD
P
32 TEST3 I
33 TEST2 I
34 TEST1 I
35 TEST0 I
36 NC
37 BREQ O
38 BACK I
39 IDREQ I
40 IDACK O
No. Pin name Type
41 AEN O
42 AST O
43 MDEN O
44 MRD O
45 MWR O
46 IORD O
47 IOWR O
48 LDE O
49 UDE O
50 READY I
51 DTC O
52 V
SS
P
53 NC
54 MA23 O
55 MA22 O
56 MA21 O
57 MA20 O
58 MA19 O
59 MA18 O
60 MA17 O
61 MA16 O
62 MA/MD15 O
63 V
SS
P
64 MA/MD14 B
65 MA/MD13 B
66 MA/MD12 B
67 MA/MD11 B
68 MA/MD10 B
69 MA/MD9 B
70 MA/MD8 B
71 MA/MD7 B
72 V
SS
P
73 V
DD
P
74 MA/MD6 B
75 MA/MD5 B
76 MA/MD4 B
77 MA/MD3 B
78 MA/MD2 B
79 MA/MD1 B
80 MA/MD0 B
AR-F152
12 – 16
To Next Page
Loading...
