Sharp LC-30HV4E - Page 46

46
LC-30HV4E
Pin No. Pin Name Type Description
1, 19, 32, 33 VDD –– Power supply
44, 64
2 PLLVDC –– PLL power supply
3 VCOIN I VCO IN (used to construct external loop filter)
4 TEST I Input for testing
5 CPOUT O Charge pump out (used to construct external loop filter)
6 PLLEN I PLL enable signal input
7 PLLGND ––
8, 9, 10, 18, 31 GND ––
41, 42, 43, 62
11 PLLENO O PLL enable signal output
12 SPDIFO O S/PDIF output (3.072 Mbps)
13 SPDIFI I S/PDIF input (3.072 Mbps)
14 IO0 I/O Expanded I/O, bit 0
15 IO1 I/O Expanded I/O, bit 1
16 IO2 I/O Expanded I/O, bit 2
17 IO3 I/O Expanded I/O, bit 3
20 IO4 I/O Expanded I/O, bit 4
21 UTEST I Input for testing
22 NANDTO O Output for testing
23 RESET I Asynchronous reset signal input
24 MEMTEST I Input for testing
25 BISTOUT O Output for testing
26 RWCLK O Expanded FIFO R/W clock
27 RSTRW O Expanded FIFO master reset
28 FEW O Expanded FIFO write enable
29 FRE O Expanded FIFO read enable
30 FD07 O Expanded FIFO data output, bit 7
34 FD06 O Expanded FIFO data output, bit 6
35 FD05 O Expanded FIFO data output, bit 5
36 FD04 O Expanded FIFO data output, bit 4
37 FD03 O Expanded FIFO data output, bit 3
38 FD02 O Expanded FIFO data output, bit 2
39 FD01 O Expanded FIFO data output, bit 1
40 FD00 O Expanded FIFO data output, bit 0
45 FD17 I Expanded FIFO data input, bit 7
46 FD16 I Expanded FIFO data input, bit 6
47 FD15 I Expanded FIFO data input, bit 5
48 FD14 I Expanded FIFO data input, bit 4
49 FD13 I Expanded FIFO data input, bit 3
50 FD12 I Expanded FIFO data input, bit 2
51 FD11 I Expanded FIFO data input, bit 1
52 FD10 I Expanded FIFO data input, bit 0
53 SDA I/O Serial communication data
54 SCS I Serial communication chip select
55 SCK I Serial communication chip select
56 I2SCLO O I2S CL output
57 I2SDAO O I2S CL output
58 I2SWSO O I2S WS output
59 I2SWSI I I2S WS input
60 I2SDAI I I2S DA input
61 I2SCLI I I2S CL input
63 REFCLK I PLL REF CLK (same input as I2SCLI)
ËRH-iXA385WJZZ (ASSY:IC2510)
DELAY
» Pin mapping