Sharp UP-600 - Page 37

2)-3. Pin description
Pin
No.
Name IN/OUT Description
1 GND - GND
2 GND - GND
3 BA7 O Address bus 7 for PB-RAM (NU)
4 BA6 O Address bus 6 for PB-RAM (NU)
5 BA5 O Address bus 5 for PB-RAM (NU)
6 BA4 O Address bus 4 for PB-RAM (NU)
7 BA3 O Address bus 3 for PB-RAM (NU)
8 BA2 O Address bus 2 for PB-RAM (NU)
9 BA1 O Address bus 1 for PB-RAM (NU)
10 GND - GND
11 BA0 O Address bus 0 for PB-RAM (NU)
12 BWR# O PB-RAM write strobe signal (NU)
13 BRD# O PB-RAM read strobe signal (NU)
14 BRAS O PB-RAM chip select : Active High (NU)
15 BRAS# O PB-RAM chip select : Active Low (NU)
16 BD7 I/O Data Bus 7 for PB-RAM (NU)
17 BD6 I/O Data Bus 6 for PB-RAM(NU)
18 BD5 I/O Data Bus 5 for PB-RAM (NU)
19 GND - GND
20 BD4 I/O Data Bus 4 for PB-RAM (NU)
21 BD3 I/O Data Bus 3 for PB-RAM (NU)
22 GND - GND
23 BD2 I/O Data Bus 2 for PB-RAM (NU)
24 BD1 I/O Data Bus 1 for PB-RAM (NU)
25 BD0 I/O Data Bus 0 for PB-RAM (NU)
26 GND - GND
27 VDD - +3.3V
28 INT3# I Interrupt signal 3 (NU)
29 INT2# I Shift enable for CKDC9
30 INT1# I Keyboard request for CKDC9
31 INT0# I Power off signal input
32 HTS1 O 8 bit serial port output (for CKDC9)
33 SCK1# O Serial port shift clock output (for CKDC9)
34 STH1 I 8 bit serial port input (for CKDC9)
35 IPLON# I IPL switch 0 ON signal
36 RESET# I MPCA reset
37 UTST# I MPCA test pin (+3.3V)
38 USEL0 I MPCA test pin (GND)
39 USEL1 I MPCA test pin (GND)
40 USEL2 I MPCA test pin (GND)
41 MCRINT O MCR interrupt signal
42 WAIT# O Wait request signal
43 FROS1# O Flash ROM 1 chip select signal
44 RASPN1 O RAM 1 chip select signal
45 RASPN2 O RAM 2 chip select signal
46 EPROM1# O EP-ROM 1 chip select signal
47 DSEX# O EP-ROM 2 chip select signal
48 RXDH O 8 bit serial port output to CPU
49 TXDH I 8 bit serial port input from CPU
50 SCKH I Serial port shift clock input from CPU
51 GND - GND
52 GND - GND
53 VDD - +3.3V
54 OSO1 O System clock (7.37MHz)
Pin
No.
Name IN/OUT Description
55 OSI1 I System clock (7.37MHz)
56 GND - GND
57 UASCK O USAT clock to CPU
58 MD1 I MPCA test pin (GND)
59 MD0 I MPCA test pin (GND)
60 PHAI I System clock (9.83MHz)
61 AS# I Address strobe
62 RD# I Read Strobe
63 WR# I Write Strobe
64 IRQ0# O Interrupt request 0 to CPU
65 IRQ1# O Interrupt request 1 to CPU
66 SSPRQ# O SSP interrupt request to CPU
67 GND - GND
68 D0 I/O Data Bus 0
69 D1 I/O Data Bus 1
70 D2 I/O Data Bus 2
71 GND - GND
72 D3 I/O Data Bus 3
73 D4 I/O Data Bus 4
74 GND - GND
75 D5 I/O Data Bus 5
76 D6 I/O Data Bus 6
77 D7 I/O Data Bus 7
78 VDD - +3.3V
79 GND - GND
80 A0 I Address bus 0
81 A1 I Address bus 1
82 A2 I Address bus 2
83 A3 I Address bus 3
84 A4 I Address bus 4
85 A5 I Address bus 5
86 A6 I Address bus 6
87 A7 I Address bus 7
88 A8 I Address bus 8
89 A9 I Address bus 9
90 A10 I Address bus 10
91 A11 I Address bus 11
92 A12 I Address bus 12
93 A13 I Address bus 13
94 A14 I Address bus 14
95 A15 I Address bus 15
96 A16 I Address bus 16
97 A17 I Address bus 17
98 A18 I Address bus 18
99 A19 I Address bus 19
100 A20 I Address bus 20
101 A21 I Address bus 21
102 A22 I Address bus 22
103 A23 I Address bus 23
104 VDD - +3.3V
105 GND - GND
106 GND - GND
107 CD5# I RS-232 ch1 CD signal
108 CI5# I RS-232 ch1 CI signal