2) DATA COMMUNICATION
Data is transmitted from the host CPU to the TCP/IP board or vice
versa through the dual-port SRAM. If data is written into the same
address of the dual-port SRAM from both sides or written into and
read from the same address from both sides, data is not assured.
The following procedure should be observed.
The format of data to be handled should meet the software specifica-
tions.
• Interrupt signals from host to board : Write/INTHW (Host Write),
Read/INTHR (Host Read)
/INTHW (Host Write) is generated by writing into the address
H’7*** of the dual-port SRAM and cancelled by outputting the
/HWACK signal by 100ns LOW pulse.
/INTHR (Host Read) is generated by reading the address H’B*** of
the dual-port SRAM and cancelled by outputting the /HRACK sig-
nal by 100ns LOW pulse.
• Interrupt signals from board to host : Write /INTSW (Slave Write),
Read /INTSR (Slave Read)
/INTSW (Slave Write) is generated by outputting the /SWRQ sig-
nal by 100ns LOW pulse and cancelled by writing data into the
address H’B*** of the dual-port SRAM from the host side..
/INTSR (Slave Read) is generated by outputting the /SRRQ signal
by 100ns low pulse and cancelled by reading data from the ad-
dress H’7*** of the dual-port SRAM.
7. LAN CONTROL
This board fixes RTL8019AS to the 8-bit mode on hardware.
The initial values of the items in the table are set as shown below by
hardware.
Item Setting Remarks
I/O Base Address 300H IOS3~0=0,0,0,0
Network Media Type TP/CX automatic
detection
PL1~0=0,0
BROM Size & Memory
Base Address
Disable BS4~0=0,0,0,0,0
IRQ Select INT0 IRQS2~0=0,0,0
Any data loading EEPROM is not used. MAC address should be
written by the CPU reading data on the flash memory and writing the
register of the LAN controller.
8. PORT SETTING
The common pins of the CPU are set as shown below.
Pin
No
I/O
Selection
signal
Remarks
2 I PE15 /WP(FLASH write STATUS)
24 I /IRQ0 Host write end interrupt (
Edge detection)
25 I /IRQ1 Host read end interrupt (
Edge detection)
26 I /IRQ2 Interrupt from LANC (
Edge detection)
28 I /IRQ3 Reserve (
Edge detection)
29 O A18 Address Bus
30 O A19 Address Bus
31 I /WAIT wait from LANC
44 O /CS3 Chip Select for LAN (Usual access space)
45 O /CS2 Chip Select for dual-port SRAM
106 O PE8 /SRRQ (Board side read end request)
107 O PE9 /SWRQ (Board side write end request)
108 O PE10 /HRACK
(host side read end interrupt cancel)
110 O PE11 /HWACK
(host side write end interrupt cancel)
112 O PE13 /RSTDRViActive Lowj
Write
Y
N
Read
Y
N
Preceding data read
end interrupt?
Write data
Generation of write
end interrupt
Data write end
interrupt?
Read data
Generation of read
end interrupt
AEN
SA19-SA0
SD7-SD0
IORB
IOWB
INT0
IOCHRDY
CPU RTL8019AS
SLOT16 GND
/CS3
A19-A0
D7-D0
/RD
/WRL
/IRQ2
/WAIT
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