Sharp ZQ-5000

ZQ-5000
ZQ-5200
(2) Circuit description
a. Main battery voltage detection
When input voltage VIN exceeds the detection voltage VD, the output
of the voltage detection IC [LBIC (MN1280)] is driven from Low to
High. When VIN falls under VD, the output is driven from High to Low.
The LBIC (MN1 280) detects both the CAU level and the STOP level
by dividing the voltage applied to the input terminal (2 pin) with Rl
and R2 and by turning on/off R2 with CAU signal of G-A.
When the power voltage falls under the CAU level, as shown in Fig.
3, the BAl7 symbol lights up. When the power voltage falls further
under the STOP level, the symbol goes off.
For CAU level detection, the CPU E9 terminal it turned on (low level)
and the CPU IRQ terminal state is observed. (If the IRQ is at Low
level, the symbol lights up.)
When the CAU level is detected, the CPU E9 terminal is turned off
(high impedance). (When the CPU E9 terminal is turned off, resistor
division is not performed and the voltage at LBIC 2 pin increases,
driving the output from Low to High.) The CPU IRQ terminal state is
checked again to detect the STOP level.
After the STOP level is detected, the ON key and the RESET key
become ineffective.
4
CPU E9
(N-ch open)
b. Memory protection battery
“CC
1
After Smsec of E8’s becoming high, DIS becomes low. After I oopsec,
the back-up battery low voltage is detected. When LBIC is high, it is
normal. When LBIC is low, KIO becomes high to turn off the display
of <ATTENTION> after 5 sec.
6. Memory map
CEI
loooot
1 aooot
2oooot
CE2
3oooot
CE5
4oooot
CEO
‘30000t
CE3
coooot
CE4
EOOOOI
00000t
04ooot
FFFFFI
DRIVER
32KS SOP IC
-Internal RAM .-.
32K8 COB
EX RAM1
54KE
EX RAM2
64 KS
EX CED
256 KS
PM)
EX CED
25s KB
(34
SYSTEM ROM
1 MB
(Internal)
04000H
qxi+$
07FFFH
E8
Backup
-9-