Technology functions
3.1 High-speed counters
CPU 1512C-1 PN (6ES7512-1CK00-0AB0)
42 Manual, 09/2016, A5E35306440-AB
Offset from start
address
Byte 10
Bit 7: Count direction (with encoder without direction signal)
– Bits 2 to 6: Reserve; bits must be set to 0
Bit 1: Reset of saved events
Bit 0: Reset of saved error states
Bits 0 to 7: Reserve; bits must be set to 0
* If values are loaded simultaneously via LD_SLOT_0 and LD_SLOT_1, the value fro
m Slot 0 is taken first internally and
then the value from Slot 1 . This may lead to unexpected intermediate states.
You can find a graphic representation of the processing of the various SLOT parameters in
the section Handling the SLOT parameter (control interface) (Page 64).
Assignment of the feedback interface of the high-speed counters
The user program receives current values and status information from the high speed
counter via the feedback interface.
Note
Operation with High_Speed_Counter technology object
The High_Speed_Counter technology object is available for high
-speed counting mode. We
therefore recommend use of the technol
ogy object High_Speed_Counter instead of the
control interface/feedback interface for controlling the high speed counter.
For information on configuring the technology object and programming the associated
instruction, refer to the S7
-1500, ET 200MP, ET 20
0SP Counting, measurement and position
detection (
http://support.automation.siemens.com/WW/view/en/59709820) function manual.
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