Technology functions
3.1 High-speed counters
CPU 1512C-1 PN (6ES7512-1CK00-0AB0)
Manual, 09/2016, A5E35306440-AB
43
Feedback interface per channel
The following table shows the feedback interface assignment:
Table 3- 4 Assignment of the feedback interface
Offset from start
address
Bytes 4 to 7 CAPTURED VALUE Last Capture value acquired
Byte 12
Bits 3 to 7: Reserve; set to 0
Bit 2: Error when loading via control interface
Bit 1: Incorrect encoder signal
Bit 0: Incorrect supply voltage L+
Byte 13
Bits 6 to 7: Reserve; set to 0
Bit 5: Software gate status
Bit 4: Digital on-board I/O started up and parameters assigned
Bit 3: Load request for Slot 1 detected and executed (toggling)
Bit 2: Load request for Slot 0 detected and executed (toggling)
Bit 1: Reset of event bits active
Byte 14
Bit 2: Internal gate status
STS_CNT Bit 1: Count pulse detected within last approx. 0.5 s
Bit 0: Direction of last count value change
Byte 15
Bit 7: Count pulse detected in previous measuring interval
Bit 6: Capture event has occurred
Bit 5: Synchronization has occurred
Bit 4: Comparison event for DQ1 has occurred
Bit 3: Comparison event for DQ0 has occurred
Bit 2: Overflow has occurred
Bit 1: Underflow has occurred
Bit 0: Zero crossing has occurred
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