Sinclair ZX Spectrum Service Manual
Spectrum For Everyone https://spectrumforeveryone.com/
11
1.5.3 32k Expansion RAM (IC15-IC32)
The eight 32k ICs making up the 32k x 8 bit expansion RAM are in fact 64k ICs with either row or column
drop-out, rendering one half of the memory non-functional. In order to accommodate the Texas
Instruments RAM (Type TMS 4532) or the optional OKI RAM (Type MSM3732) a set of links are provided,
visible on the circuit diagram above the address multiplexer IC25/IC26. These links not only cater for the
different manufacturer (Issue 3 Spectrums only) but also allow, in both instances, one of the two IC
versions to be selected depending on which half of the RAM (top, bottom, left or right) is functional. The
links are respectively TI and OKI (manufacturer - Issue 3 Spectrums only), -3/-4 (TI version) and -H/-L (OKI
version - Issue 3 Spectrums only).
NOTE: It is essential when replacing ICs in this area that all RAMs carry the same manufacturers part
number and that all links are selected accordingly.
The expansion RAM is organised as a matrix of 128 rows x 256 columns (TI RAMs) or 256 rows x 128 (OKI
RAMs). Thus, separate 7/8 bit row and column addresses are required to access any of these locations.
These addresses are supplied by the CPU on address bus A14-A0 via an address multiplexer IC25/IC26. For
example, when accessing the TI RAM, the low order address bits A6 to A0 give the row address; AR is held
low on the -3 version selecting the top half of the memory and high on the -4 version selecting the bottom
half. The column address is given by the high order address bits A14-A7.
Row/column address selection and RAS/CAS timing for the RAM is decoded in IC23/IC24 from inputs
supplied by the CPU, i.e. address line A15 selecting addresses 8000 upwards, and MREQ heralding a
memory read or write cycle. A theoretical timing diagram is shown on the next page.
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