Skyworks Si5338 - Output Clock Dividers

Si5338-RM
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9.9. Output Clock Dividers
The output clock dividers (R
x
) allow a final stage of division. The division ratio is configurable using registers 31-34
as shown in Figure 18. These dividers can be useful for generating clocks below the 5
MHz frequency limit of the
MultiSynth dividers (M
x
). Note that when using a division value other than 1, the outputs may not be in phase. If
using the part in zero delay mode then make sure all Rx dividers for all outputs that are to be zero delay, as well as
the divider for the feedback output, are set to 1.
Figure 18. Setting Output Clock Dividers
32[7:0]
01234567
33[7:0]
01234567
34[7:0]
01234567
31[7:0]
R0DIV[2:0]
01234567
R1DIV[2:0]
R2DIV[2:0]
R3DIV[2:0]
RxDIV[2:0]
x=0,1,2,3
001
010
011
100
101
2
Output Divider Value
4
8
16
32
110
Reserved
111
Reserved
000
1