Skyworks Si5338 - Page 7

Si5338-RM
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3.1.2. Sorting the Frequency Plans to Minimize Jitter
The following guidelines help to sort the frequency plans:
1. Use MSn divider values that are integers as much as possible.
2. Look for a MultiSynth value that is an integer on important output channels or frequencies.
3. Pick plans with VCO frequencies (f
vco
) close to 2.5 GHz.
3.1.3. Using Fractions to Store the MultiSynth Values
One possible problem, when implementing this algorithm, is losing precision or introducing rounding errors in the
calculations. To prevent this and to better model the operation of the MultiSynths, use a data structure where the
type will have three parts: integer or whole number, numerator and denominator. Using 64-bit unsigned numbers
yields high precision in the fraction and more than what the Si5338 supports. Additionally, use this data structure to
store the input and output frequencies, MultiSynth values, VCO frequency, and phase detector frequency.
Operations like addition, subtraction, division, multiplication, simplifying the fraction, and even comparisons like
equal-to, greater-than and less-than are necessary to implement the algorithm.
3.1.4. Truncating MultiSynth Values
If the MultiSynth reduced fractional values (numerator and denominator) do not fit in the corresponding bit fields in
the register map, truncation is necessary. Truncation implies that some of the desired frequencies are not
achievable with the specified precision.
First check if the MSn divider needs to be truncated (that is, the numerator or denominator of MSn is greater than
2
30
– 1). If it does, truncate the f
vco
and recalculate the MSn. The f
vco
should stay within the allowed range.
When the MultiSynth dividers (MSx) are calculated after the f
vco
is calculated with the above procedure, check if
the dividers need to be truncated (the numerator or denominator is greater than 2
30
– 1). If so, divide the numerator
and denominator of the affected MultiSynth by 2 until both the numerator and denominator fit (this is equivalent to
bit-shifting to reduce the length of the variable to 30 bits). The division can be done on the actual MultiSynth values,
not the P2 or P3 numbers for the registers. Of course, the denominator should not be zero.