48-TERMINAL, HTQFP PACKAGE (TOP VIEW)
SSTIMER
OC_ADJ
PLL_FLTP
VR_ANA
NC
AVSS
PLL_FLTM
BST_A
GVDD_OUT
PVDD_A
OUT_A
RESET
PVDD_A
STEST
PDN
VR_DIG
OSC_RES
DVSSO
DVDD
MCLK
FAULT
SCLK
SDIN
LRCLK
AVDD
SDA
SCL
DVSS
GND
VREG
BST_B
PVDD_B
PVDD_C
OUT_C
PVDD_D
BST_D
PGND_AB
OUT_B
PGND_CD
OUT_D
AGND
PGND_AB
PVDD_B
PGND_CD
PVDD_D
BST_C
PVDD_C
GVDD_OUT
P0075-01
PHP Package
(Top View)
TAS5707
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TAS5707
SLOS556A–NOVEMBER 2008 – REVISED APRIL 2009 .................................................................................................................................................
www.ti.com
PIN FUNCTIONS
PIN
TYPE 5-V TERMINATION
DESCRIPTION
(1)
TOLERANT
(2)
NAME NO.
AGND 30 P Analog ground for power stage
AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 43 P High-side bootstrap supply for half-bridge B
BST_C 42 P High-side bootstrap supply for half-bridge C
BST_D 33 P High-side bootstrap supply for half-bridge D
DVDD 27 P 3.3-V digital power supply
DVSSO 17 P Oscillator ground
DVSS 28 P Digital ground
GND 29 P Analog ground for power stage
GVDD_OUT 5, 32 P Gate drive internal regulator output
LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master clock input
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups ĺ logic 1 input; pulldowns ĺ logic 0 input).
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5707
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