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Sony CHC-P11 - Page 34

Sony CHC-P11
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HCD-H11/H11J
|
IC
BLOCK
DIAGRAMS
-TCB
SECTION-—
IC
BLOCK
DIAGRAMS
-MAIN
SECTION-
1C21
LC72130
1C104
M62423FP
PO2
Or
AUT?
aim?
Li
mic
tm
IN?
UWBASS?
WEBASS2
«—-FBASS?
feo?
=o
NEMIO?
=F
mIO?
FIRED
oe
¥ee2
VSS
x0ut
Lg
@)
Al
>
a
sw
MUTE
>
m =
(+)
C+}-—('5)
(0)
(9)
0)
(+) (3)
ce
DATA
LATCH
«WOO
Jon
HBAS]
-WOASST
«FDASSI
tmetes
«omMIDY
«Fes
FIRED
oes
tear
a)
ee)
Se
Gn
IN
805
ct
o
a
00
401
402
003
toe
To.
1Fin
1C105
TC9210P
1C41
LA1835
=z
«
e
¢
re
5
3
=
»
2:
L-CH
-
?
t
t
8
.
3
°
x
.
e
, :
@
4
2
4
8
@
$
§
38
8
&$
«
4
an
an
ice
DECODER
ANTI
BERDIE
{\
eames
Bay
tee
Note
:
¢
All
capacitors
are
in
uF
unless
otherwise
noted.
pF:
uyuF
5OWV
or
less
are
not
indicated
except
for
electrolytics
and
tantalums.
All
resistors
are
in
Q
and
‘/sW
or
less
unless
otherwise
specified.
*
A:
internal
component.
1€106,402
BL1641
1C971
.PC1237HA
.
:
B+
Line
*([__]}:
adjustment
for
repair.
*
Voltage
and
waveforms
are
dc
with
respect
to
ground
under
no-signal
(
detuned
)
conditions.
de
ie
ceuk
(
):
AM
LATCH
AUTORESET
*
Voltages
are
taken
with
a
VOM
(
Input
impedance
10M).
Voltage
variations
may
be
noted
due
to
normal
production
cage
tolerances.
FWO/REV/STOP
¢
Waveforms
are
taken
with
a
oscilloscope.
CONTROL
LOGIC
f
Voltage
variations
may
be
noted
due
to
normal
production
tolerances.
4)
;
2
45
&
2
=X
-~
S™
SS
*
Signal
path.
&
pian
(fences
<
:
ray
GO
Se
Bz
oa
ow
a
a
>
u
u
ou
oa
xro
z=
(e)
Pa
wW
>
>
Zin
ro
>>
:FM
uw
a
«
.
=>
AM
ae
as
42
43

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