Sony HCD-AZ5D - Schematic Diagram - S-MASTER Board (2;4)

4848
HCD-AZ2D/AZ5D
HCD-AZ2D/AZ5D
7-22. SCHEMATIC DIAGRAM – S-MASTER BOARD (2/4) –
• See page 59 for Waveforms. • See page 62 for IC Block Diagrams.
C796
L519
R560 R561
R553
R554
R569
C749
C569
R562
L516
C783
FB702
IC515
IC518
IC506
R510
R677
R685
R787
R791FL505
FL506
C794
C795
C785
C786 C787
R630
R617
R588
R564
R563
R546
R545
R539
R535
R532
R531
R529
R525
R524
R520
R518
IC505
IC504
C689
C688
C687
C599
C598
C597
C561
C560
C559
C558
C557
C550
C549
C548
C547
C546
C545
C544
C537
R523
R522
R521
R517
R528
R542
R541
R543
R551
R550
R552
C563
R
5
5
7
R
5
5
6
R
5
5
8
R555
EP506
EP507
L518
L517
C562
EP505
C628
C556
R536
R537
R538
EP501
C536
C543
R533
R540
R527
R547
C747
C748
C780
C781
C782
C570C503
X502
R786
R600
C784
100
10V
00
0
0
0
100
10V
100p
0
0
22
25V
0
MC74VHC1GU04
NJM2870F18
CXD9788AR
0
10k
10k
100
100
0.1
0.01
5p
0.001 10p
10k
10k
1k
0
0
0
0
0
10k
0
0
1k
0
0
10k
1k
CXD9788AR
CXD9788AR
100
10V
0.1
0.1
100
10V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
1k
1k
1k
100
1k
1k
1k
1k
1k
1k
1k
0.1
1
k
1
k
1
k
10k
(CHASSIS) (CHASSIS)
(CHASSIS)
0
0
0.1
(CHASSIS)
0.1
100p
1k
1k
1k
0.1
100p
1k
0
100
1k
0.1
0.1
0.1
0.1
0.1
0.10.1
49.152MHz
1M
100
0.01
1
30
20
19
2
3
4
5
6
8
7
9
10
11
12
13
14
29
28
27
26
25
24
23
22
21
36
35
34
33
32
31
51
SCK
INIT
SCK
INIT
SCK
NSP MUTE
SCDT
SCSHIFT
LAT3
OVF
LAT1
SCSHIFT
SCDT
NSP MUTE
LAT2
SCSHIFT
SCDT
NSP MUTE
INIT
I
STREAM PROCESSOR
STREAM PROCESSOR
STREAM PROCESSOR
+1.8V REGULATOR
CLOCK BUFFER
VI
VO
CN
T
G
ND
N.B.
VDD
NC GND
(AZ5D)
(2/4)
(AZ5D)
1µH
(Page 50)
(Page 47)
(Page 49)
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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