Sony HCD-CP1 - IC Block Diagrams

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– 36 –
• IC Block Diagrams
– MAIN Board –
IC101, 201 TDA7296
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY-GND
IN– IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS –VS
STBY
MUTE
NC NC
+PWVS
OUT
–PWVS
14 1512 1310 118 96 753 41 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
IC301 TDA7439
VREF
VOLUME
TREBLE
MIDDLE
BASS
SPEAKER
ATTENUATOR
MULTIPLEXER
GAIN AMP
IIC BUS
DECODER &
LATCH
SUPPLY
SDA
CREF
VS
AGND
ROUT
LOUT
SCL DIG GND TREBLE (R) TREBLE (L) MIN (L) MOUT (L) BOUT (L) BIN (L) BOUT (R) BIN (R) MOUT (R) MIN (R) INR
1 2 3 4 5 6
R-IN4 R-IN3
7 8
R-IN2 R-IN1
9 10
MULTIPLEXER
GAIN AMP
L-IN1 L-IN2
11 12
L-IN3 L-IN4
13 14
MUX OUT (L)
15
18
VOLUME
TREBLE
MIDDLE
BASS
SPEAKER
ATTENUATOR
INL MUX OUT (R)
161727282930 22 21 20 1926 25 24 23
IC309 KA3082
GND
OUT1
VCTL
VZ1 VZ2
IN1 IN2
VCC1 VCC2
OUT2
5 6 7 8 9 101 2 3 4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
IC804 BU1924F-E2 (AEP, UK models)
ANALOG
DIGITAL
RCLK NC XO XI
VSS2
T2
VDD2
T1
QUAL
RDAT
VREF
MUX
VDD1
VSS1 VSS3
CMP
1 43 65 872
141516 13 12
11
10 9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST