Sony HCD-CP300 - IC Block Diagrams

37
HCD-CP300
IC603 BU1924AF (MAIN BOARD)
IC602 µPD7225G (MAIN BOARD)
IC101, 201 TDA7296 (MAIN BOARD)
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY-GND
IN– IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS –VS
STBY
MUTE
NC NC
+PWVS
OUT
–PWVS
14 1512 1310 118 96 753 41 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
1 2 3 4 5 6 7 8
910111213141516
QUAL
RDATA
VREF
VDD1
VSS1
MUX
VSS3
CMP
RCLK XO XI (NC) VDD2 VSS2 T1 T2
8TH SWITCHED
CAPACITOR
FILTER
PLL 57KHz
RDS/ARI
BIPHASE
DECODER
DEFFERENTIAL
DECODER
PLL
1187.5Hz
TEST
CLOCK
3
V 1
4
5
2
LCD
TIMING
CONTROL
OSC
WRITE CONTROL
BLINKING
DATA
MEMORY
DATA
POINTER
DATA
MEMORY
SEGMENT
DECODER
52
6
13
CL1
1
CL2
COM3
SIRIAL INTERFACE
COMMAND / DATA REGISTER
19 – 32 , 34 – 51
S0 – S13 , S14 – S31
7, 33
LC
V
DD
V
SS
V 2
LC
V 3
LC
SYNC
RESET
9
18
COM2
17
COM1
16
COM0
15
SI
8
SCK
6
13
V
SS
RESET
13
RESET
COMMAND
DECODER
LCD DRIVER
DESPLAY DATA LATCH
6-21. IC BLOCK DIAGRAMS