Sony SPP-A1071 - DIAGRAMS; Block Diagram - Base Unit

SPP-A1070/A1071
1111
SECTION 5
DIAGRAMS
5-1. BLOCK DIAGRAM – BASE UNIT Section –
RX DATA
RLL DATA
RLL CLK
RLL EN
CAR DET
TX DATA
15
1
2
3
4
5
6
14
11
12
B+ SWITCH
(FOR LEDS)
Q12
MAIL BOX
1
PLAY/STOP
MAIL BOX
1
PLAY/STOP
7 SEGMENTS
LED DRIVE
Q10, 11
9
10
11
24
23
22
20
1
2
34
31
21
20
26
27
28
19
23
24
33
4 3 2 1 44
21
13
14
10
9
8
25
12
3
2
1
4
16
4
5
AF AMP
(FOR RX)
U2 (2/4)
AF AMP
(FOR DTMF)
U2 (3/4)
LINE DC
COMPARATOR
U2 (4/4)
RINGER
DETECT
U7
HOOK ON/OFF
DETECT
Q9
CHARGE
DETECT
Q3, 4
+5V
REGULATOR
U5
RESET SIGNAL
GENERATOR
Q5, 6
+
–
CHARGE
TERMINAL
DC IN 9V
–
+
J3
29
30
14
AF AMP
(FOR TX)
U2 (1/4)
SPEAKER
AMP
U9
BUFFER
Q1
D7
KEY MATRIX
KP1, 2, 4 – 11,
KP13, 15, 16
LINE
J1
HOOK ON/OFF
U1
B+ (+5V)
D1 – D4
RECT
D3 D1
D4 D2
T1
LINE TRANSFORMER
FREQUENCY SHIFT
KEYING DEMODULATOR
U3
X1
3.58MHz
7 SEGMENTS LED
(MESSAGE COUNTER)
U1
LED1
B+
(+5V)
LED2 LED3 LED4
LED/7 SEGMENTS LED
DRIVER
U10
B+
(+5V)
A1
RF UNIT
I-TAD UNIT
+
+
SP101
SYSTEM
CONTROLLER
U4
D11, 12
ANT LINE TX
MIC LIFPOUT
SPK OUT LIF MIN1
SP EN
ROW0 – ROW4
COL0 – COL2
HOOK SW
BU HOOK
RING DET
LED SEL
L DATA
L CLK
L LATCH
7SEG D1
7SEG D2
LINE DC
RX DATA
PLL DATA
PLL CLK
TX DATA
LINE RX
PLL EN
CAR DET
A
SHIF
CLK
LATCH
CLK
QA
QB
QC
QD
QE
QF
QG
DTMF
OUT
XIN
XOUT
IN SE
IN P
IN N
M DAT
SCK
SD IN
INT
DCB RD
DC COMPA
SD OUT
IN DSP
IN DCN
RX DATA
PLL DATA
PLL CLK
PLL EN
CAR DET
TX DATA
PAGE
IN USE-LED
CHARGE-LED
NEW CALL-LED
DO
CLK
CS
DI
OFF HOOK
PARK
FST CHG
RESET
DI
CLK
CS
DO
RX DATA
PLL DATA
PLL CLK
PLL EN
CAR DET
TX DATA
DCB RD
DCA
CIDINT
CIDSDA
CIDSCL
SI
MUTING
Q13
MIC
MIC101
REC/MEMO
ANSWER
ON/OFF
KP1
ERASE
VOLUME
KP7
MENU
KP10
SELECT
KP9
TIME/SET
KP8
KP2
3
KP6
2
KP5
–
KP15
+
KP16
KP4
SLOW
REPEAT
KP11
QUICK
SKIP
KP13
ANSWER
ON/OFF
HANDSET
LOCATOR
2 3
KP17
NEW CALL
LED7
LINE
LED6
CHARGE
LED5
EEPROM
U6
B+ SWITCH
Q2
CHARGE
CONTROL
Q7, 8
• SIGNAL PATH
: TX
: RX
: BELL
X2
8MHz
1615
XOUT XIN