ST STM32F401 User Manual

Hardware layout UM1669
14/39 DocID025174 Rev 1
Figure 5. STM32F401VCT6 block diagram
GPIO PORT A
AHB/APB2
EXT IT. WKUP
up to 81 AF
PA[15:0]
TIM1 / PWM
4 compl. channels TIM1_CH1[1:4]N,
4 channels TIM1_CH1[1:4]ETR,
BKIN as AF
USART1
RX, TX, CK,
CTS, RTS as AF
SPI1
MOSI, MISO,
SCK, NSS as AF
APB2 60MHz
APB1 30MHz
16 analog inputs
VDDREF_ADC
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
SP3/I2S3
ALARM_OUT
OSC32_IN
OSC32_OUT
VDDA, VSSA
NRST
smcard
irDA
16b
VBAT = 1.65 to 3.6 V
DMA2
SCL, SDA, SMBA as AF
I2C3/SMBUS
JTAG & SW
ARM Cortex-M4
84 MHz
NVIC
ETM
MPU
TRACECLK
TRACED[3:0]
DMA2
8 Streams
FIFO
ACCEL/
CACHE
AHB1 84 MHz
USART 2MBps
Temperature sensor
ADC1
IF
@VDDA
POR/PDR
BOR
Supply
supervision
@VDDA
PVD
Int
POR
reset
XTAL 32 kHz
MANAGT
RTC
RC HS
RC LS
PWR
interface
WDG 32K
@V
BAT
@VDDA
@VDD
AWU
Reset &
clock
control
PLL1&2
APB2CLK
VDD = 1.7 to 3.6 V
VSS
VCAP
Voltage
regulator
3.3 to 1.2 V
VDD
Power managmt
@VDD
STAMP1
Backup register
AHB bus-matrix 7S4M
APB2 84 MHz
LS
TIM9
2 channels as AF
Flash
up to
256 KB
TIM2
TIM3
TIM4
TIM5
D-BUS
MS31144V2
FPU
APB1 42 MHz (max)
AHB2 84 MHz
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
I-BUS
S-BUS
DMA1
8 Streams
FIFO
PB[15:0]
PC[15:0]
PH[1:0]
GPIO PORT B
GPIO PORT C
GPIO PORT H
16b
TIM10
16b
TIM11
16b
smcard
irDA
USART6
1 channel as AF
1 channel as AF
RX, TX, CK as AF
I2C2/SMBUS
I2C1/SMBUS
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SP2/I2S2
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
RX, TX as AF
CTS, RTS as AF
USART2
smcard
irDA
32b
16b
16b
32b
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
DMA1
AHB/APB1
LS
OSC_IN
OSC_OUT
HCLK
XTAL OSC
4- 16MHz
SRAM 64 KB
WWDG
APB1CLK
AHB1PCLK
AHB2PCLK
CRC
(PDR OFF)
1.8 to 3.6 V
(PDR ON)
SDIO / MMC
FIFO
D[7:0]
CMD, CK as AF
USB
OTG FS
FIFO
PHY
DP
DM
ID, VBUS, SOF
SPI4
MOSI, MISO,
SCK, NSS as AF
PD[15:0]
GPIO PORT D
PE[15:0]
GPIO PORT E

ST STM32F401 Specifications

General

Brand	ST
Model	STM32F401
Category	Microcontrollers
Language	English