Clocks AN4938
22/48 DocID029918 Rev 1
3.3 Clock security system (CSS)
The device provides two clock security systems (CSS), one for HSE oscillator and one for
LSE oscillator. They can be independently enabled by software.
When the clock security system on HSE is enabled, the clock detector is activated after the
HSE oscillator startup delay, and disabled when this oscillator is stopped:
• If the HSE oscillator is used directly or indirectly as the system clock (indirectly
meaning that it is directly used as PLL input clock, and that PLL clock is the system
clock) and a failure is detected, then the system clock switches to the HSI oscillator and
the HSE oscillator is disabled.
• If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timers TIM1, TIM8, TIM15,
TIM16, and TIM17, and a non-maskable interrupt is generated to inform the software
about the failure (clock security system interrupt rcc_hsecss_it), allowing the MCU to
perform rescue operations. The rcc_hsecss_it is linked to the Cortex
®
-M7 NMI (non-
maskable interrupt) exception vector.
• If the HSE oscillator clock was used as PLL clock source, the PLL is also disabled
when the HSE fails.
The clock security system on LSE must be enabled only when the LSE is enabled and
ready, and after the RTC clock has been selected through the RTCSRC[1:0] bits of
RCC_BDCR register.
When an LSE failure is detected, the CSS on LSE wakes up the device from all low-power
modes except V
BAT
. If the failure occurred in V
BAT
mode, the software can check the failure
detection bit when the device is powered on again. In all cases the software can select the
best behavior (including disabling the CSS on LSE which is not automatic).
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